DESIGN OF A PATTERN CLUSTER USING TWO-LEVEL PIPELINED SYSTOLIC ARRAY.

A systolic architecture is presented for squared-error pattern clustering. The systolic pattern clustering array can offload from the host the time-consuming pattern clustering tasks. The host will provide the initial cluster centers. Given a number of cluster centers, the systolic pattern clustering array will result in a partition of the patterns among clusters. Depending on the heuristic used, the host may add, delete, or merge the clusters and initialize another clustering task. The processing time for one pass evaluation of the new cluster centers is dominated by the memory cycles required to fetch the pattern matrix once. It is a systolic architecture because data flows from the memory modules in a rhythmic fashion, passing through many processing units before it returns to the memory. It is a two-level pipelined design because each processing unit is also pipelined. The modularity and the regularity of the system architecture make it suited to VLSI implementations.