Efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms

Xiao Dong Zhang; Chi Ying Tsui

Efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms

Xiao Dong Zhang^*
, Chi Ying Tsui

^*Corresponding author for this work

Research output: Contribution to journal › Conference article published in journal › peer-review

6 Citations (Scopus)

Abstract

This paper describes a VLSI architecture which can be reconfigured to support both Full Search Block-Matching algorithm and 3-step Hierarchical Search Block-Matching algorithm. By using a reconfigurable register-mux array and a parameterizable adder tree, the 2-D array architecture provides efficient real time motion estimation for many video applications. We also propose a memory architecture and an associated switching network to solve the simultaneous data access problem.

Original language	English
Pages (from-to)	603-606
Number of pages	4
Journal	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume	1
Publication status	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP. Part 1 (of 5) - Munich, Ger Duration: 21 Apr 1997 → 24 Apr 1997

Cite this

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title = "Efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms",

abstract = "This paper describes a VLSI architecture which can be reconfigured to support both Full Search Block-Matching algorithm and 3-step Hierarchical Search Block-Matching algorithm. By using a reconfigurable register-mux array and a parameterizable adder tree, the 2-D array architecture provides efficient real time motion estimation for many video applications. We also propose a memory architecture and an associated switching network to solve the simultaneous data access problem.",

author = "Zhang, \{Xiao Dong\} and Tsui, \{Chi Ying\}",

year = "1997",

language = "English",

volume = "1",

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journal = "ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings",

issn = "0736-7791",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP. Part 1 (of 5) ; Conference date: 21-04-1997 Through 24-04-1997",

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AU - Zhang, Xiao Dong

AU - Tsui, Chi Ying

PY - 1997

Y1 - 1997

N2 - This paper describes a VLSI architecture which can be reconfigured to support both Full Search Block-Matching algorithm and 3-step Hierarchical Search Block-Matching algorithm. By using a reconfigurable register-mux array and a parameterizable adder tree, the 2-D array architecture provides efficient real time motion estimation for many video applications. We also propose a memory architecture and an associated switching network to solve the simultaneous data access problem.

AB - This paper describes a VLSI architecture which can be reconfigured to support both Full Search Block-Matching algorithm and 3-step Hierarchical Search Block-Matching algorithm. By using a reconfigurable register-mux array and a parameterizable adder tree, the 2-D array architecture provides efficient real time motion estimation for many video applications. We also propose a memory architecture and an associated switching network to solve the simultaneous data access problem.

UR - https://www.scopus.com/pages/publications/0030681714

M3 - Conference article published in journal

AN - SCOPUS:0030681714

SN - 0736-7791

VL - 1

SP - 603

EP - 606

JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

T2 - Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP. Part 1 (of 5)

Y2 - 21 April 1997 through 24 April 1997

ER -

Efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms

Abstract

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