Efficient systolic designs for 1- and 2-Dimensional DFT of general transform-lengths for high-speed wireless communication applications

Pramod K. Meher, Jagdish C. Patra, A. P. Vinod

Research output: Contribution to journalJournal Articlepeer-review

10 Citations (Scopus)

Abstract

In wireless communication, multiple receive-antennas are used with orthogonal frequency division multiplexing (OFDM) to improve the system capacity and performance. The discrete Fourier transform (DFT) plays an important part in such a system since the DFTs are required to be performed for the output of all those antennas separately. This paper presents area-time efficient systolic structures for one-dimensional (1-D) and two-dimensional (2-D) DFTs of general lengths. A low-complexity recursive algorithm based on Clenshaw's recurrence relation is formulated for the computation of 1-D DFT. The proposed algorithm is used further to derive a linear systolic array for the DFT. The concurrency of computation has been enhanced and complexity is minimized by the proposed algorithm where an N-point DFT is computed via four inner-products of real-valued data of length ≈(N/2). The proposed 1-D structure offers significantly lower latency, twice the throughput, and involves nearly the same area-time complexity of the corresponding existing structures. The proposed algorithm for 1-D DFT is extended further to obtain a 2-D systolic structure for the 2-D DFT without involving any transposition operation.

Original languageEnglish
Pages (from-to)1-14
Number of pages14
JournalJournal of Signal Processing Systems
Volume60
Issue number1
DOIs
Publication statusPublished - Jul 2010
Externally publishedYes

Keywords

  • DFT
  • Systolic array
  • VLSI

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