Efficient test methodologies for high-speed serial links

As devices become increasingly complex and faster, high-speed serial interfaces such as PCI-Express, SerialATA, XAUI and others are proliferating. Several trends in semiconductor technologies accelerate the adoption of serial interfaces, in order to mitigate the high pin-count and the data-channel skewing problems. In this section, we describe the basics of operation and test of high-speed serial links. High-speed serial links are composed of a transmitter (TX) and a receiver (RX) communicating over a channel. Figure 1.1 shows the typical block diagram of a transceiver for high-speed serial links. Due to the limited number of I/O pins in a chip and density constraints on the number of wires between the chips, the links usually convert parallel data to serial one using a serializer before transmitting the data. In the receiver side, this serial data is reconverted to the original parallel data using a deserializer. A clock and data recovery (CDR) circuit in the receiver extracts the clock information from the data to synchronize the receiver with the incoming data because, in serial communication systems, the clock signal is embedded in the data. Thus, the CDR circuit plays a critical role in determining the quality of serial communication systems, including influencing metrics such as bit error rate (BER). As the data rates continue to increase and approach speed of multi-gigabits/second the signal is distorted by the bandwidth limitation of the channel. In order to compensate for channel loss, a pre-emphasis at the TX and an equalizer at the RX are implemented in the system. In addition, a simple pattern generator and an error detector are found in most transceiver designs for testing purposes.