Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

Fen Ge; Jia Zhan; Yuan Xie; Vijaykrishnan Narayanan

doi:10.1109/ISQED.2015.7085489

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

3 Citations (Scopus)

Abstract

Network-on-Chip (NoC) provides a scalable approach to integrate more and more cores on chip, while limited capacity and bandwidth of DRAMs becomes the performance bottleneck. To break the memory wall, 3D integration of DRAMs and processors using Through Silicon Vias (TSVs) has emerged. Distributed memory controllers (MCs) are allocated on chip in order to utilize the abundant bandwidth of stacked DRAMs, but unavoidably incur significant hardware overhead. In this paper, we analyze the design of memory controllers in NoC-based many-core systems with stack-DRAMs. By analyzing the interaction between NoCs and MCs, the optimal number and placement of MCs are explored. Specifically, a Genetic algorithm (GA) based approach is proposed to find the optimal memory controller placement with different number of DRAM partitions. We evaluate memory controller configurations for various memory-intensive applications in terms of network latency and energy, as well as thermal distribution.

Original language	English
Title of host publication	Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
Publisher	IEEE Computer Society
Pages	565-570
Number of pages	6
ISBN (Electronic)	9781479975815
DOIs	https://doi.org/10.1109/ISQED.2015.7085489
Publication status	Published - 13 Apr 2015
Externally published	Yes
Event	16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States Duration: 2 Mar 2015 → 4 Mar 2015

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2015-April
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	16th International Symposium on Quality Electronic Design, ISQED 2015
Country/Territory	United States
City	Santa Clara
Period	2/03/15 → 4/03/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

3D Integration
Network-on-Chip
memory controller

Access to Document

10.1109/ISQED.2015.7085489

Cite this

Ge, F., Zhan, J., Xie, Y., & Narayanan, V. (2015). Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015 (pp. 565-570). Article 7085489 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2015-April). IEEE Computer Society. https://doi.org/10.1109/ISQED.2015.7085489

@inproceedings{9ad28a743a7b41949aea1f79d97085c0,

title = "Exploring memory controller configurations for many-core systems with 3D stacked DRAMs",

abstract = "Network-on-Chip (NoC) provides a scalable approach to integrate more and more cores on chip, while limited capacity and bandwidth of DRAMs becomes the performance bottleneck. To break the memory wall, 3D integration of DRAMs and processors using Through Silicon Vias (TSVs) has emerged. Distributed memory controllers (MCs) are allocated on chip in order to utilize the abundant bandwidth of stacked DRAMs, but unavoidably incur significant hardware overhead. In this paper, we analyze the design of memory controllers in NoC-based many-core systems with stack-DRAMs. By analyzing the interaction between NoCs and MCs, the optimal number and placement of MCs are explored. Specifically, a Genetic algorithm (GA) based approach is proposed to find the optimal memory controller placement with different number of DRAM partitions. We evaluate memory controller configurations for various memory-intensive applications in terms of network latency and energy, as well as thermal distribution.",

keywords = "3D Integration, Network-on-Chip, memory controller",

author = "Fen Ge and Jia Zhan and Yuan Xie and Vijaykrishnan Narayanan",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 16th International Symposium on Quality Electronic Design, ISQED 2015 ; Conference date: 02-03-2015 Through 04-03-2015",

year = "2015",

month = apr,

day = "13",

doi = "10.1109/ISQED.2015.7085489",

language = "English",

series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

publisher = "IEEE Computer Society",

pages = "565--570",

booktitle = "Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015",

}

Ge, F, Zhan, J, Xie, Y & Narayanan, V 2015, Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. in Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015., 7085489, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2015-April, IEEE Computer Society, pp. 565-570, 16th International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, United States, 2/03/15. https://doi.org/10.1109/ISQED.2015.7085489

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. / Ge, Fen; Zhan, Jia; Xie, Yuan et al.
Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society, 2015. p. 565-570 7085489 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2015-April).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

AU - Ge, Fen

AU - Zhan, Jia

AU - Xie, Yuan

AU - Narayanan, Vijaykrishnan

PY - 2015/4/13

Y1 - 2015/4/13

N2 - Network-on-Chip (NoC) provides a scalable approach to integrate more and more cores on chip, while limited capacity and bandwidth of DRAMs becomes the performance bottleneck. To break the memory wall, 3D integration of DRAMs and processors using Through Silicon Vias (TSVs) has emerged. Distributed memory controllers (MCs) are allocated on chip in order to utilize the abundant bandwidth of stacked DRAMs, but unavoidably incur significant hardware overhead. In this paper, we analyze the design of memory controllers in NoC-based many-core systems with stack-DRAMs. By analyzing the interaction between NoCs and MCs, the optimal number and placement of MCs are explored. Specifically, a Genetic algorithm (GA) based approach is proposed to find the optimal memory controller placement with different number of DRAM partitions. We evaluate memory controller configurations for various memory-intensive applications in terms of network latency and energy, as well as thermal distribution.

AB - Network-on-Chip (NoC) provides a scalable approach to integrate more and more cores on chip, while limited capacity and bandwidth of DRAMs becomes the performance bottleneck. To break the memory wall, 3D integration of DRAMs and processors using Through Silicon Vias (TSVs) has emerged. Distributed memory controllers (MCs) are allocated on chip in order to utilize the abundant bandwidth of stacked DRAMs, but unavoidably incur significant hardware overhead. In this paper, we analyze the design of memory controllers in NoC-based many-core systems with stack-DRAMs. By analyzing the interaction between NoCs and MCs, the optimal number and placement of MCs are explored. Specifically, a Genetic algorithm (GA) based approach is proposed to find the optimal memory controller placement with different number of DRAM partitions. We evaluate memory controller configurations for various memory-intensive applications in terms of network latency and energy, as well as thermal distribution.

KW - 3D Integration

KW - Network-on-Chip

KW - memory controller

UR - https://openalex.org/W2086553016

UR - https://www.scopus.com/pages/publications/84944314768

U2 - 10.1109/ISQED.2015.7085489

DO - 10.1109/ISQED.2015.7085489

M3 - Conference Paper published in a book

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 565

EP - 570

BT - Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015

PB - IEEE Computer Society

T2 - 16th International Symposium on Quality Electronic Design, ISQED 2015

Y2 - 2 March 2015 through 4 March 2015

ER -

Ge F, Zhan J, Xie Y, Narayanan V. Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. IEEE Computer Society. 2015. p. 565-570. 7085489. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2015.7085489

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this