TY - GEN
T1 - Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory
AU - Sun, Guangyu
AU - Kursun, Eren
AU - Rivers, Jude A.
AU - Xie, Yuan
PY - 2011
Y1 - 2011
N2 - Spin-transfer Torque Random Access Memory (STT-RAM) emerges for on-chip memory in microprocessor architectures. Thanks to the magnetic field based storage STT-RAM cells have immunity to radiation induced soft errors that affect electrical charge based data storage, which is a major challenge in SRAM based caches in current microprocessors. In this study we explore the soft error resilience benefits and design trade offs of 3D-stacked STT-RAM for multi-core architectures. We use 3D stacking as an enabler for modular integration of STT-RAM caches with minimum disruption in the baseline processor design flow, while providing further interconnectivity and capacity advantages. We take an in-depth look at alternative replacement schemes in terms of performance, power, temperature, and reliability trade-offs to capture the multi-variable optimization challenges microprocessor architectures face. We analyze and compare the characteristics of STT-RAM, SRAM, and DRAM alternatives for various levels of the cache hierarchy in terms of reliability.
AB - Spin-transfer Torque Random Access Memory (STT-RAM) emerges for on-chip memory in microprocessor architectures. Thanks to the magnetic field based storage STT-RAM cells have immunity to radiation induced soft errors that affect electrical charge based data storage, which is a major challenge in SRAM based caches in current microprocessors. In this study we explore the soft error resilience benefits and design trade offs of 3D-stacked STT-RAM for multi-core architectures. We use 3D stacking as an enabler for modular integration of STT-RAM caches with minimum disruption in the baseline processor design flow, while providing further interconnectivity and capacity advantages. We take an in-depth look at alternative replacement schemes in terms of performance, power, temperature, and reliability trade-offs to capture the multi-variable optimization challenges microprocessor architectures face. We analyze and compare the characteristics of STT-RAM, SRAM, and DRAM alternatives for various levels of the cache hierarchy in terms of reliability.
UR - https://openalex.org/W2047074089
UR - https://www.scopus.com/pages/publications/83455219881
U2 - 10.1109/ICCD.2011.6081425
DO - 10.1109/ICCD.2011.6081425
M3 - Conference Paper published in a book
SN - 9781457719523
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 366
EP - 372
BT - 2011 IEEE 29th International Conference on Computer Design, ICCD 2011
T2 - 29th IEEE International Conference on Computer Design 2011, ICCD 2011
Y2 - 9 November 2011 through 12 November 2011
ER -