Fast IP table lookup and memory reduction

Y. C. Liu; C. T. Lea

doi:10.1109/HPSR.2001.923637

Fast IP table lookup and memory reduction

Y. C. Liu^*, C. T. Lea

^*Corresponding author for this work

Office of the Dean of Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

3 Citations (Scopus)

Abstract

One of the time-consuming tasks in IP4 packet processing is maximum sequence matching. Fast routing requires tens of millions of routing lookups to be performed in one second. This paper describes an implementation of IP table loop-up. The implementation is intended as part of the cord of an OC-192 (10 Gbps) and OC-768 (40 Gbps) rate packet processor. One key element is a memory reduction technique that applies to all lookup algorithms. For algorithms with similar complexity as the one described in the paper, the improvement in terms of memory reduction is about 20%∼30%.

Original language	English
Title of host publication	2001 IEEE Workshop on High Performance Switching and Routing
Pages	228-232
Number of pages	5
DOIs	https://doi.org/10.1109/HPSR.2001.923637
Publication status	Published - 2001
Event	2001 IEEE Workshop on High Performance Switching and Routing - Dallas, TX, United States Duration: 29 May 2001 → 31 May 2001

Publication series

Name	2001 IEEE Workshop on High Performance Switching and Routing

Conference

Conference	2001 IEEE Workshop on High Performance Switching and Routing
Country/Territory	United States
City	Dallas, TX
Period	29/05/01 → 31/05/01

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10.1109/HPSR.2001.923637

Cite this

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title = "Fast IP table lookup and memory reduction",

abstract = "One of the time-consuming tasks in IP4 packet processing is maximum sequence matching. Fast routing requires tens of millions of routing lookups to be performed in one second. This paper describes an implementation of IP table loop-up. The implementation is intended as part of the cord of an OC-192 (10 Gbps) and OC-768 (40 Gbps) rate packet processor. One key element is a memory reduction technique that applies to all lookup algorithms. For algorithms with similar complexity as the one described in the paper, the improvement in terms of memory reduction is about 20\%∼30\%.",

author = "Liu, \{Y. C.\} and Lea, \{C. T.\}",

year = "2001",

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series = "2001 IEEE Workshop on High Performance Switching and Routing",

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AU - Lea, C. T.

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N2 - One of the time-consuming tasks in IP4 packet processing is maximum sequence matching. Fast routing requires tens of millions of routing lookups to be performed in one second. This paper describes an implementation of IP table loop-up. The implementation is intended as part of the cord of an OC-192 (10 Gbps) and OC-768 (40 Gbps) rate packet processor. One key element is a memory reduction technique that applies to all lookup algorithms. For algorithms with similar complexity as the one described in the paper, the improvement in terms of memory reduction is about 20%∼30%.

AB - One of the time-consuming tasks in IP4 packet processing is maximum sequence matching. Fast routing requires tens of millions of routing lookups to be performed in one second. This paper describes an implementation of IP table loop-up. The implementation is intended as part of the cord of an OC-192 (10 Gbps) and OC-768 (40 Gbps) rate packet processor. One key element is a memory reduction technique that applies to all lookup algorithms. For algorithms with similar complexity as the one described in the paper, the improvement in terms of memory reduction is about 20%∼30%.

UR - https://www.scopus.com/pages/publications/0035785850

U2 - 10.1109/HPSR.2001.923637

DO - 10.1109/HPSR.2001.923637

M3 - Conference Paper published in a book

AN - SCOPUS:0035785850

SN - 0780367111

T3 - 2001 IEEE Workshop on High Performance Switching and Routing

SP - 228

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BT - 2001 IEEE Workshop on High Performance Switching and Routing

T2 - 2001 IEEE Workshop on High Performance Switching and Routing

Y2 - 29 May 2001 through 31 May 2001

ER -

Fast IP table lookup and memory reduction

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