Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation

Gerhard Schrom; Peter Hazucha; Jae Hong Hahn; Volkan Kursun; Donald Gardner; Siva Narendra; Tanay Karnik; Vivek De

doi:10.1109/LPE.2004.241035

Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation

Gerhard Schrom
, Peter Hazucha
, Jae Hong Hahn
, Volkan Kursun
, Donald Gardner
, Siva Narendra
, Tanay Karnik
, Vivek De

Research output: Contribution to journal › Conference article published in journal › peer-review

13 Citations (Scopus)

Abstract

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

Original language	English
Article number	1349348
Pages (from-to)	263-268
Number of pages	6
Journal	Proceedings of the International Symposium on Low Power Electronics and Design
Volume	2004-January
Issue number	January
DOIs	https://doi.org/10.1109/LPE.2004.241035
Publication status	Published - 2004
Externally published	Yes
Event	2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States Duration: 9 Aug 2004 → 11 Aug 2004

Bibliographical note

Publisher Copyright:
© 2004 ACM.

Keywords

3-D integration
DC-DC converter
integrated magnetics
on-die switching converter
power delivery

Access to Document

10.1109/LPE.2004.241035

Cite this

Schrom, G., Hazucha, P., Hahn, J. H., Kursun, V., Gardner, D., Narendra, S., Karnik, T., & De, V. (2004). Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation. Proceedings of the International Symposium on Low Power Electronics and Design, 2004-January(January), 263-268. Article 1349348. https://doi.org/10.1109/LPE.2004.241035

@article{d4320c64dd3a45a29c5badbf18b2ca09,

title = "Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation",

abstract = "Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85\% efficiency and 10\% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5\% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.",

keywords = "3-D integration, DC-DC converter, integrated magnetics, on-die switching converter, power delivery",

author = "Gerhard Schrom and Peter Hazucha and Hahn, \{Jae Hong\} and Volkan Kursun and Donald Gardner and Siva Narendra and Tanay Karnik and Vivek De",

note = "Publisher Copyright: {\textcopyright} 2004 ACM.; 2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 ; Conference date: 09-08-2004 Through 11-08-2004",

year = "2004",

doi = "10.1109/LPE.2004.241035",

language = "English",

volume = "2004-January",

pages = "263--268",

journal = "Proceedings of the International Symposium on Low Power Electronics and Design",

issn = "1533-4678",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "January",

}

Schrom, G, Hazucha, P, Hahn, JH, Kursun, V, Gardner, D, Narendra, S, Karnik, T & De, V 2004, 'Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation', Proceedings of the International Symposium on Low Power Electronics and Design, vol. 2004-January, no. January, 1349348, pp. 263-268. https://doi.org/10.1109/LPE.2004.241035

Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation. / Schrom, Gerhard; Hazucha, Peter; Hahn, Jae Hong et al.
In: Proceedings of the International Symposium on Low Power Electronics and Design, Vol. 2004-January, No. January, 1349348, 2004, p. 263-268.

Research output: Contribution to journal › Conference article published in journal › peer-review

TY - JOUR

T1 - Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation

AU - Schrom, Gerhard

AU - Hazucha, Peter

AU - Hahn, Jae Hong

AU - Kursun, Volkan

AU - Gardner, Donald

AU - Narendra, Siva

AU - Karnik, Tanay

AU - De, Vivek

PY - 2004

Y1 - 2004

N2 - Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

AB - Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

KW - 3-D integration

KW - DC-DC converter

KW - integrated magnetics

KW - on-die switching converter

KW - power delivery

UR - https://openalex.org/W7117653386

UR - https://www.scopus.com/pages/publications/84886673002

U2 - 10.1109/LPE.2004.241035

DO - 10.1109/LPE.2004.241035

M3 - Conference article published in journal

AN - SCOPUS:84886673002

SN - 1533-4678

VL - 2004-January

SP - 263

EP - 268

JO - Proceedings of the International Symposium on Low Power Electronics and Design

JF - Proceedings of the International Symposium on Low Power Electronics and Design

IS - January

M1 - 1349348

T2 - 2004 International Symposium on Low Power Electronics and Design, ISLPED 2004

Y2 - 9 August 2004 through 11 August 2004

ER -

Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation

Abstract

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this