Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

Q. Y. Tong; T. H. Lee; W. J. Kim; T. Y. Tan; U. Goesele; H. M. You; W. Yun; Johnny K.O. Sin

Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

Q. Y. Tong^*
, T. H. Lee
, W. J. Kim
, T. Y. Tan
, U. Goesele
, H. M. You
, W. Yun
, Johnny K.O. Sin

^*Corresponding author for this work

Research output: Contribution to conference › Conference Paper › peer-review

16 Citations (Scopus)

Abstract

The feasibility of using plasma enhanced chemical vapor deposition TEOS (PETEOS) oxide and associated chemical mechanical polishing (CMP)to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding was evaluated. Results show that the PETEOS oxide can be used to create a very strong bond after annealing at temperatures as low as 300 °C.

Original language	English
Pages	36-37
Number of pages	2
Publication status	Published - 1996
Externally published	Yes
Event	Proceedings of the 1996 IEEE International SOI Conference - Sanibel Island, FL, USA Duration: 30 Sept 1996 → 3 Oct 1996

Conference

Conference	Proceedings of the 1996 IEEE International SOI Conference
City	Sanibel Island, FL, USA
Period	30/09/96 → 3/10/96

Cite this

@conference{c72ac72e2c09472dbbb71fbab061b11b,

title = "Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding",

abstract = "The feasibility of using plasma enhanced chemical vapor deposition TEOS (PETEOS) oxide and associated chemical mechanical polishing (CMP)to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding was evaluated. Results show that the PETEOS oxide can be used to create a very strong bond after annealing at temperatures as low as 300 °C.",

author = "Tong, \{Q. Y.\} and Lee, \{T. H.\} and Kim, \{W. J.\} and Tan, \{T. Y.\} and U. Goesele and You, \{H. M.\} and W. Yun and Sin, \{Johnny K.O.\}",

year = "1996",

language = "English",

pages = "36--37",

note = "Proceedings of the 1996 IEEE International SOI Conference ; Conference date: 30-09-1996 Through 03-10-1996",

}

TY - CONF

T1 - Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

AU - Tong, Q. Y.

AU - Lee, T. H.

AU - Kim, W. J.

AU - Tan, T. Y.

AU - Goesele, U.

AU - You, H. M.

AU - Yun, W.

AU - Sin, Johnny K.O.

PY - 1996

Y1 - 1996

N2 - The feasibility of using plasma enhanced chemical vapor deposition TEOS (PETEOS) oxide and associated chemical mechanical polishing (CMP)to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding was evaluated. Results show that the PETEOS oxide can be used to create a very strong bond after annealing at temperatures as low as 300 °C.

AB - The feasibility of using plasma enhanced chemical vapor deposition TEOS (PETEOS) oxide and associated chemical mechanical polishing (CMP)to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding was evaluated. Results show that the PETEOS oxide can be used to create a very strong bond after annealing at temperatures as low as 300 °C.

UR - https://www.scopus.com/pages/publications/0030394560

M3 - Conference Paper

AN - SCOPUS:0030394560

SP - 36

EP - 37

T2 - Proceedings of the 1996 IEEE International SOI Conference

Y2 - 30 September 1996 through 3 October 1996

ER -

Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

Abstract

Conference

Other files and links

Fingerprint

Cite this