GaN on Engineered Bulk Silicon Power Integration Platform With Avalanche Capability Enabled by Built-in Si PN Junctions

Gang Lyu, Sirui Feng, Li Zhang, Tao Chen, Jin Wei, Kevin J. Chen*

*Corresponding author for this work

Research output: Contribution to journalJournal Articlepeer-review

6 Citations (Scopus)

Abstract

A GaN on engineered bulk silicon (GaN-on-EBUS) power IC platform featuring an industry-standard 200-V GaN power HEMT epi-structure has been recently demonstrated, showing effective isolation and crosstalk suppression between the high-side (HS) and low-side (LS) GaN transistors in half-bridge configuration. In this work, we scale up the vertical breakdown voltage (BV ) of the GaN film on the EBUS substrate to be over 600 V. Meanwhile, the built-in back-to-back PN junctions along the trench created in the Si substrate are employed to provide an overvoltage-protection scheme through their intrinsic avalanche capability for the overlaying GaN half-bridge circuit.

Original languageEnglish
Pages (from-to)1826-1829
Number of pages4
JournalIEEE Electron Device Letters
Volume43
Issue number11
DOIs
Publication statusPublished - 1 Nov 2022

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

  • Monolithic GaN power integration
  • PN junction
  • bulk silicon substrate
  • half bridge circuit

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