Handling variations and uncertainties

Tim Cheng

doi:10.1109/MDT.2006.148

Handling variations and uncertainties

Tim Cheng

Office of the Vice-President for Research and Development

Research output: Contribution to journal › Editorial

Abstract

With increased technology scaling, high variability and low reliability will likely be the main challenges for chip design and testing. This issue discusses some of the key issues for handling increasing variations and uncertainties. Also, D&T's plans for 2007 special themes have been finalized.

Original language	English
Pages (from-to)	434
Number of pages	1
Journal	IEEE Design and Test of Computers
Volume	23
Issue number	6
DOIs	https://doi.org/10.1109/MDT.2006.148
Publication status	Published - Nov 2006

Keywords

Reliability
Statistical design
Test process
Variation

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10.1109/MDT.2006.148

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@article{eba45d1950f04b57a3744aebc8306bb3,

title = "Handling variations and uncertainties",

abstract = "With increased technology scaling, high variability and low reliability will likely be the main challenges for chip design and testing. This issue discusses some of the key issues for handling increasing variations and uncertainties. Also, D\&T's plans for 2007 special themes have been finalized.",

keywords = "Reliability, Statistical design, Test process, Variation",

author = "Tim Cheng",

year = "2006",

month = nov,

doi = "10.1109/MDT.2006.148",

language = "English",

volume = "23",

pages = "434",

journal = "IEEE Design and Test of Computers",

issn = "0740-7475",

publisher = "IEEE Computer Society",

number = "6",

}

TY - JOUR

T1 - Handling variations and uncertainties

AU - Cheng, Tim

PY - 2006/11

Y1 - 2006/11

N2 - With increased technology scaling, high variability and low reliability will likely be the main challenges for chip design and testing. This issue discusses some of the key issues for handling increasing variations and uncertainties. Also, D&T's plans for 2007 special themes have been finalized.

AB - With increased technology scaling, high variability and low reliability will likely be the main challenges for chip design and testing. This issue discusses some of the key issues for handling increasing variations and uncertainties. Also, D&T's plans for 2007 special themes have been finalized.

KW - Reliability

KW - Statistical design

KW - Test process

KW - Variation

UR - https://www.webofscience.com/wos/woscc/full-record/WOS:000242725200001

UR - https://openalex.org/W2154698240

U2 - 10.1109/MDT.2006.148

DO - 10.1109/MDT.2006.148

M3 - Editorial

SN - 0740-7475

VL - 23

SP - 434

JO - IEEE Design and Test of Computers

JF - IEEE Design and Test of Computers

IS - 6

ER -

Handling variations and uncertainties

Abstract

Keywords

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