Abstract
Low-power and high-speed implementation of discrete cosine transform (DCT) for mobile multimedia terminals presents a hardware design challenge. The cost of DCT implementation is dominated by the complexity of the multiplier. The systolic array and the memory-based designs do not consider the optimization of the multiplications in transform coding. A method to minimize the complexity of multiplication in DCT by efficient sharing of the common subexpressions that occur in the canonic signed digit (CSD) representation of the elements of the DCT matrix is presented here. Design example of a 8×8 DCT using 16 bits shows that our method offers hardware reduction of 38% over conventional method.
| Original language | English |
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| Pages | A227-A230 |
| DOIs | |
| Publication status | Published - 2004 |
| Externally published | Yes |
| Event | IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering - Chiang Mai, Thailand Duration: 21 Nov 2004 → 24 Nov 2004 |
Conference
| Conference | IEEE TENCON 2004 - 2004 IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering |
|---|---|
| Country/Territory | Thailand |
| City | Chiang Mai |
| Period | 21/11/04 → 24/11/04 |