High-Current E-Mode InGaN/GaN p-FET on p-GaN Gate HEMT Platform

Jingjing Yu; Jin Wei; Junjie Yang; Teng Li; Han Yang; Yingming Song; Jiawei Cui; Sihang Liu; Xuelin Yang; Maojun Wang; Bo Shen

doi:10.1109/LED.2024.3520582

High-Current E-Mode InGaN/GaN p-FET on p-GaN Gate HEMT Platform

Jingjing Yu, Jin Wei^*, Junjie Yang, Teng Li, Han Yang, Yingming Song, Jiawei Cui, Sihang Liu, Xuelin Yang, Maojun Wang, Bo Shen^*

^*Corresponding author for this work

Research output: Contribution to journal › Journal Article › peer-review

8 Citations (Scopus)

Abstract

The low current density in E-mode GaN p-FET presents a severe challenge for its application in complementary logic (CL) circuits. In this work, a high-current E-mode InGaN/GaN p-FET is demonstrated on a p-GaN gate HEMT platform with p-InGaN/p-GaN/AlGaN/GaN heterostructure. The proposed heterostructure introduces a net polarization charge at the InGaN/GaN interface, leading to an enhanced 2DHG. With a negative gate bias, a buried 2DHG channel is formed prior to the surface MIS channel. As a result, the recess-gate InGaN/GaN p-FET with L_G = 2μm achieves a large maximum current (I_max) exceeding -20 mA/mm. The InGaN/GaN p-FET obtains a low R_ON of 0.64 kΩ ·mm and a high I_ON/I_OFF ratio exceeding 10⁷. The device presents E-mode operation with a threshold voltage (V_TH) of -1.8 V and a low subthreshold swing (SS) of 144 mV/dec. Furthermore, an E-mode n-channel GaN HEMT is fabricated on the same platform, validating the potential of the proposed InGaN/GaN p-FET for GaN CL circuits.

Original language	English
Pages (from-to)	139-142
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	46
Issue number	2
DOIs	https://doi.org/10.1109/LED.2024.3520582
Publication status	Published - 2025
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 1980-2012 IEEE.

Keywords

E-mode
GaN complementary logic
InGaN p-FET
InGaN/GaN p-FET
two-dimensional hole gas (2DHG)

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10.1109/LED.2024.3520582

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title = "High-Current E-Mode InGaN/GaN p-FET on p-GaN Gate HEMT Platform",

abstract = "The low current density in E-mode GaN p-FET presents a severe challenge for its application in complementary logic (CL) circuits. In this work, a high-current E-mode InGaN/GaN p-FET is demonstrated on a p-GaN gate HEMT platform with p-InGaN/p-GaN/AlGaN/GaN heterostructure. The proposed heterostructure introduces a net polarization charge at the InGaN/GaN interface, leading to an enhanced 2DHG. With a negative gate bias, a buried 2DHG channel is formed prior to the surface MIS channel. As a result, the recess-gate InGaN/GaN p-FET with LG = 2μm achieves a large maximum current (Imax) exceeding -20 mA/mm. The InGaN/GaN p-FET obtains a low RON of 0.64 kΩ ·mm and a high ION/IOFF ratio exceeding 107. The device presents E-mode operation with a threshold voltage (VTH) of -1.8 V and a low subthreshold swing (SS) of 144 mV/dec. Furthermore, an E-mode n-channel GaN HEMT is fabricated on the same platform, validating the potential of the proposed InGaN/GaN p-FET for GaN CL circuits.",

keywords = "E-mode, GaN complementary logic, InGaN p-FET, InGaN/GaN p-FET, two-dimensional hole gas (2DHG)",

author = "Jingjing Yu and Jin Wei and Junjie Yang and Teng Li and Han Yang and Yingming Song and Jiawei Cui and Sihang Liu and Xuelin Yang and Maojun Wang and Bo Shen",

note = "Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",

year = "2025",

doi = "10.1109/LED.2024.3520582",

language = "English",

volume = "46",

pages = "139--142",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - High-Current E-Mode InGaN/GaN p-FET on p-GaN Gate HEMT Platform

AU - Yu, Jingjing

AU - Wei, Jin

AU - Yang, Junjie

AU - Li, Teng

AU - Yang, Han

AU - Song, Yingming

AU - Cui, Jiawei

AU - Liu, Sihang

AU - Yang, Xuelin

AU - Wang, Maojun

AU - Shen, Bo

PY - 2025

Y1 - 2025

N2 - The low current density in E-mode GaN p-FET presents a severe challenge for its application in complementary logic (CL) circuits. In this work, a high-current E-mode InGaN/GaN p-FET is demonstrated on a p-GaN gate HEMT platform with p-InGaN/p-GaN/AlGaN/GaN heterostructure. The proposed heterostructure introduces a net polarization charge at the InGaN/GaN interface, leading to an enhanced 2DHG. With a negative gate bias, a buried 2DHG channel is formed prior to the surface MIS channel. As a result, the recess-gate InGaN/GaN p-FET with LG = 2μm achieves a large maximum current (Imax) exceeding -20 mA/mm. The InGaN/GaN p-FET obtains a low RON of 0.64 kΩ ·mm and a high ION/IOFF ratio exceeding 107. The device presents E-mode operation with a threshold voltage (VTH) of -1.8 V and a low subthreshold swing (SS) of 144 mV/dec. Furthermore, an E-mode n-channel GaN HEMT is fabricated on the same platform, validating the potential of the proposed InGaN/GaN p-FET for GaN CL circuits.

AB - The low current density in E-mode GaN p-FET presents a severe challenge for its application in complementary logic (CL) circuits. In this work, a high-current E-mode InGaN/GaN p-FET is demonstrated on a p-GaN gate HEMT platform with p-InGaN/p-GaN/AlGaN/GaN heterostructure. The proposed heterostructure introduces a net polarization charge at the InGaN/GaN interface, leading to an enhanced 2DHG. With a negative gate bias, a buried 2DHG channel is formed prior to the surface MIS channel. As a result, the recess-gate InGaN/GaN p-FET with LG = 2μm achieves a large maximum current (Imax) exceeding -20 mA/mm. The InGaN/GaN p-FET obtains a low RON of 0.64 kΩ ·mm and a high ION/IOFF ratio exceeding 107. The device presents E-mode operation with a threshold voltage (VTH) of -1.8 V and a low subthreshold swing (SS) of 144 mV/dec. Furthermore, an E-mode n-channel GaN HEMT is fabricated on the same platform, validating the potential of the proposed InGaN/GaN p-FET for GaN CL circuits.

KW - E-mode

KW - GaN complementary logic

KW - InGaN p-FET

KW - InGaN/GaN p-FET

KW - two-dimensional hole gas (2DHG)

UR - https://www.webofscience.com/wos/woscc/full-record/WOS:001410884800014

UR - https://www.scopus.com/pages/publications/85212965019

U2 - 10.1109/LED.2024.3520582

DO - 10.1109/LED.2024.3520582

M3 - Journal Article

SN - 0741-3106

VL - 46

SP - 139

EP - 142

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 2

ER -

High-Current E-Mode InGaN/GaN p-FET on p-GaN Gate HEMT Platform

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Keywords

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