Hot-Carrier Current Modeling and Device Degradation in Surface-Channel p-MOSFET's

The channel field and substrate current models developed for n-MOSFET's are applicable to p-MOSFET's. The impact ionization rate extracted for holes is found to be 8 x 106 exp (-3.7 x 106/E), where E is the electric field. Using the lucky electron approach, the gate current of surface-channel (SC) p-MOSFET's has been successfully modeled. Device degradation in p-MOSFET's is due to trapped electrons in the oxide. p-MOSFET lifetime has good correlation with gate current in SC p-MOSFET's. The correlation is better than with substrate current. IG can be larger in a buried-channel (BC) p-MOSFET than in a comparable SC n-MOSFET. This makes the SC MOSFET a much more reliable device. Device lifetime of a p-MOSFET under pulse stress can be predicted from dc stress data for inverterlike waveforms. For other waveforms, there is an extra degradation probably caused by the excess hot carriers generated during the gate turn-off transient.