Abstract
DC lifetime, in conjunction with speed and time factors, can be used to predict digital circuit hot-carrier lifetime. Analog circuit reliability prediction, on the other hand, has to take analog design variables such as channel length, biasing conditions, and circuit topography into consideration. We propose a new methodology for predicting analog circuit reliability. Instead of the traditional lifetime plots, we present a set of analog hot-carrier design curves that span the analog design space. The design curves will become increasingly important for high speed analog applications and for ULSI chips that integrate a wide variety of analog and digital functions. The design curves can be used to quickly estimate the hot-carrier sensitivity of a particular analog sub-block and to adjust the design variables for better hot-carrier immunity.
| Original language | English |
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| Title of host publication | 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 168-172 |
| Number of pages | 5 |
| ISBN (Electronic) | 0780309782 |
| DOIs | |
| Publication status | Published - 1993 |
| Externally published | Yes |
| Event | 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan, Province of China Duration: 12 May 1993 → 14 May 1993 |
Publication series
| Name | International Symposium on VLSI Technology, Systems, and Applications, Proceedings |
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| ISSN (Print) | 1930-8868 |
Conference
| Conference | 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 |
|---|---|
| Country/Territory | Taiwan, Province of China |
| City | Taipei |
| Period | 12/05/93 → 14/05/93 |
Bibliographical note
Publisher Copyright:© 1993 IEEE.