Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells

Hong Zhu; Volkan Kursun

doi:10.1109/ISQED.2013.6523650

Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells

Hong Zhu
, Volkan Kursun

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

1 Citation (Scopus)

Abstract

Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing supply voltage in scaled CMOS technologies. A selected set of novel seven-transistor (7T) and conventional six-transistor (6T) multi-threshold-voltage memory circuits are characterized for data stability, write margin, and idle mode leakage currents with an equal area constraint under parameter variations in this paper. The mean of the statistical read static noise margin distribution is enhanced by up to 2.4X and the mean of the statistical array leakage power consumption distribution is reduced by up to 82% with the triple-threshold-voltage 7T SRAM cells as compared to the traditional 6T SRAM cells in a UMC 80nm CMOS technology.

Original language	English
Title of host publication	Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013
Pages	448-453
Number of pages	6
DOIs	https://doi.org/10.1109/ISQED.2013.6523650
Publication status	Published - 2013
Event	14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA, United States Duration: 4 Mar 2013 → 6 Mar 2013

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	14th International Symposium on Quality Electronic Design, ISQED 2013
Country/Territory	United States
City	Santa Clara, CA
Period	4/03/13 → 6/03/13

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

battery lifetime
data stability
energy efficiency
leakage power consumption
Noise immunity
process variations
supply voltage variations
write margin

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10.1109/ISQED.2013.6523650

Cite this

Zhu, H., & Kursun, V. (2013). Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells. In Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013 (pp. 448-453). Article 6523650 (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2013.6523650

@inproceedings{3ea790e188ff4d738906c5fbba61f73c,

title = "Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells",

abstract = "Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing supply voltage in scaled CMOS technologies. A selected set of novel seven-transistor (7T) and conventional six-transistor (6T) multi-threshold-voltage memory circuits are characterized for data stability, write margin, and idle mode leakage currents with an equal area constraint under parameter variations in this paper. The mean of the statistical read static noise margin distribution is enhanced by up to 2.4X and the mean of the statistical array leakage power consumption distribution is reduced by up to 82\% with the triple-threshold-voltage 7T SRAM cells as compared to the traditional 6T SRAM cells in a UMC 80nm CMOS technology.",

keywords = "battery lifetime, data stability, energy efficiency, leakage power consumption, Noise immunity, process variations, supply voltage variations, write margin",

author = "Hong Zhu and Volkan Kursun",

year = "2013",

doi = "10.1109/ISQED.2013.6523650",

language = "English",

isbn = "9781467349536",

series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

pages = "448--453",

booktitle = "Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013",

note = "14th International Symposium on Quality Electronic Design, ISQED 2013 ; Conference date: 04-03-2013 Through 06-03-2013",

}

Zhu, H & Kursun, V 2013, Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells. in Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013., 6523650, Proceedings - International Symposium on Quality Electronic Design, ISQED, pp. 448-453, 14th International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, United States, 4/03/13. https://doi.org/10.1109/ISQED.2013.6523650

Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells. / Zhu, Hong; Kursun, Volkan.
Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. 2013. p. 448-453 6523650 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells

AU - Zhu, Hong

AU - Kursun, Volkan

PY - 2013

Y1 - 2013

N2 - Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing supply voltage in scaled CMOS technologies. A selected set of novel seven-transistor (7T) and conventional six-transistor (6T) multi-threshold-voltage memory circuits are characterized for data stability, write margin, and idle mode leakage currents with an equal area constraint under parameter variations in this paper. The mean of the statistical read static noise margin distribution is enhanced by up to 2.4X and the mean of the statistical array leakage power consumption distribution is reduced by up to 82% with the triple-threshold-voltage 7T SRAM cells as compared to the traditional 6T SRAM cells in a UMC 80nm CMOS technology.

AB - Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing supply voltage in scaled CMOS technologies. A selected set of novel seven-transistor (7T) and conventional six-transistor (6T) multi-threshold-voltage memory circuits are characterized for data stability, write margin, and idle mode leakage currents with an equal area constraint under parameter variations in this paper. The mean of the statistical read static noise margin distribution is enhanced by up to 2.4X and the mean of the statistical array leakage power consumption distribution is reduced by up to 82% with the triple-threshold-voltage 7T SRAM cells as compared to the traditional 6T SRAM cells in a UMC 80nm CMOS technology.

KW - battery lifetime

KW - data stability

KW - energy efficiency

KW - leakage power consumption

KW - Noise immunity

KW - process variations

KW - supply voltage variations

KW - write margin

UR - https://www.scopus.com/pages/publications/84879559588

U2 - 10.1109/ISQED.2013.6523650

DO - 10.1109/ISQED.2013.6523650

M3 - Conference Paper published in a book

AN - SCOPUS:84879559588

SN - 9781467349536

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 448

EP - 453

BT - Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013

T2 - 14th International Symposium on Quality Electronic Design, ISQED 2013

Y2 - 4 March 2013 through 6 March 2013

ER -

Zhu H, Kursun V. Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells. In Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013. 2013. p. 448-453. 6523650. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2013.6523650

Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells

Abstract

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UN SDGs

Keywords

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