TY - GEN
T1 - Improved differential coefficients-based low power FIR filters
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
AU - Vinod, A. P.
AU - Chang, Chip Hong
AU - Singla, Ankita
PY - 2006
Y1 - 2006
N2 - This paper and its companion paper (entitled Part II - Algorithm) together present techniques for low power realization of finite impulse response (FIR) filters using improved differential coefficients method (DCM). This paper presents the necessary foundation and terminology of the DCM. The companion paper describes our algorithm and presents design examples. In contrast to the conventional DCM that is formulated at the algorithm-level, our method is formulated at the architecture-level using dedicated shift-andadd-based coefficient multipliers in order to achieve considerable hardware reduction. By employing a differential coefficient-partitioning algorithm (DCPA), we show that the number of full adders and the net memory needed to implement the coefficient multipliers can be significantly reduced. The proposed method is combined with common subexpression elimination method for further reduction of complexity. Experimental results show the average reductions of full adder, memory and energy dissipated achieved by our method over the DCM are 40%, 35% and 50% respectively.
AB - This paper and its companion paper (entitled Part II - Algorithm) together present techniques for low power realization of finite impulse response (FIR) filters using improved differential coefficients method (DCM). This paper presents the necessary foundation and terminology of the DCM. The companion paper describes our algorithm and presents design examples. In contrast to the conventional DCM that is formulated at the algorithm-level, our method is formulated at the architecture-level using dedicated shift-andadd-based coefficient multipliers in order to achieve considerable hardware reduction. By employing a differential coefficient-partitioning algorithm (DCPA), we show that the number of full adders and the net memory needed to implement the coefficient multipliers can be significantly reduced. The proposed method is combined with common subexpression elimination method for further reduction of complexity. Experimental results show the average reductions of full adder, memory and energy dissipated achieved by our method over the DCM are 40%, 35% and 50% respectively.
UR - https://www.scopus.com/pages/publications/34547324422
U2 - 10.1109/ISCAS.2006.1692661
DO - 10.1109/ISCAS.2006.1692661
M3 - Conference Paper published in a book
AN - SCOPUS:34547324422
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 617
EP - 620
BT - ISCAS 2006
Y2 - 21 May 2006 through 24 May 2006
ER -