Abstract
Hardware prefetching plays a critical role in hiding the off-chip DRAM latency. The complexity of applications results in a wide variety of memory access patterns, prompting the development of numerous cache-prefetching algorithms. Consequently, commercial processors often employ a hybrid of these algorithms to enhance the overall prefetching performance. Nonetheless, since these prefetchers share hardware resources, conflicts arising from competing prefetching requests can negate the benefits of hardware prefetching. Under such circumstances, several prefetcher selection algorithms have been proposed to mitigate conflicts between prefetchers. However, these prior solutions suffer from two limitations. First, the input demand request allocation is inaccurate. Second, the prefetcher selection criteria are coarse-grained. In this paper, we address both limitations by introducing an efficient and widely applicable prefetcher selection algorithm - Alecto 1, which tailors the demand requests for each prefetcher. Every demand request is first sent to Alecto to identify suitable prefetchers before being routed to prefetchers for training and prefetching. Our analysis shows that Alecto is adept at not only harmonizing prefetching accuracy, coverage, and timeliness but also significantly enhancing the utilization of the prefetcher table, which is vital for temporal prefetching. Alecto outperforms the state-of-the-art RL-based prefetcher selection algorithm - Bandit by 2.76% in single-core, and {7. 5 6%} in eight-core. For memory-intensive benchmarks, Alecto outperforms Bandit by {5. 2 5%}. Alecto consistently delivers state-of-the-art performance in scheduling various types of cache prefetchers. In addition to the performance improvement, Alecto can reduce the energy consumption associated with accessing the prefetchers' table by 48% (7% energy reduction on the entire memory hierarchy), while only adding less than 1 KB of storage overhead.1The name Alecto stands for the combination of selection and allocation.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2025 IEEE International Symposium on High Performance Computer Architecture, HPCA 2025 |
| Publisher | IEEE Computer Society |
| Pages | 204-216 |
| Number of pages | 13 |
| ISBN (Electronic) | 9798331506476 |
| ISBN (Print) | 9798331506483 |
| DOIs | |
| Publication status | Published - 2025 |
| Event | 31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025 - Las Vegas, United States Duration: 1 Mar 2025 → 5 Mar 2025 |
Publication series
| Name | Proceedings - International Symposium on High-Performance Computer Architecture |
|---|---|
| ISSN (Print) | 1530-0897 |
| ISSN (Electronic) | 2378-203X |
Conference
| Conference | 31st IEEE International Symposium on High Performance Computer Architecture, HPCA 2025 |
|---|---|
| Country/Territory | United States |
| City | Las Vegas |
| Period | 1/03/25 → 5/03/25 |
Bibliographical note
Publisher Copyright:© 2025 IEEE.
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