Integration challenges of III-V materials in advanced CMOS logic

R. J.W. Hill; J. Huang; W. Y. Loh; T. Kim; M. H. Wong; D. Veksler; T. H. Cunningham; R. Droopad; J. Oh; C. Hobbs; P. D. Kirsch; R. Jammy

doi:10.1149/1.3700951

Integration challenges of III-V materials in advanced CMOS logic

R. J.W. Hill^*, J. Huang, W. Y. Loh, T. Kim, M. H. Wong, D. Veksler, T. H. Cunningham, R. Droopad, J. Oh, C. Hobbs, P. D. Kirsch, R. Jammy

^*Corresponding author for this work

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

Abstract

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with X_j<10nm, N_D>5× 10¹⁹cm^-3, ρ_c= 6 Ω.μm² and D_it= 4 ×10¹²cV^-1.cm^-2.

Original language	English
Title of host publication	Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2
Publisher	Electrochemical Society Inc.
Pages	179-184
Number of pages	6
Edition	6
ISBN (Electronic)	9781607683162
ISBN (Print)	9781566779586
DOIs	https://doi.org/10.1149/1.3700951
Publication status	Published - 2012
Externally published	Yes
Event	International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting - Seattle, WA, United States Duration: 6 May 2012 → 10 May 2012

Publication series

Name	ECS Transactions
Number	6
Volume	45
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting
Country/Territory	United States
City	Seattle, WA
Period	6/05/12 → 10/05/12

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Cite this

Hill, R. J. W., Huang, J., Loh, W. Y., Kim, T., Wong, M. H., Veksler, D., Cunningham, T. H., Droopad, R., Oh, J., Hobbs, C., Kirsch, P. D., & Jammy, R. (2012). Integration challenges of III-V materials in advanced CMOS logic. In Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 (6 ed., pp. 179-184). (ECS Transactions; Vol. 45, No. 6). Electrochemical Society Inc.. https://doi.org/10.1149/1.3700951

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title = "Integration challenges of III-V materials in advanced CMOS logic",

abstract = "The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.",

author = "Hill, \{R. J.W.\} and J. Huang and Loh, \{W. Y.\} and T. Kim and Wong, \{M. H.\} and D. Veksler and Cunningham, \{T. H.\} and R. Droopad and J. Oh and C. Hobbs and Kirsch, \{P. D.\} and R. Jammy",

year = "2012",

doi = "10.1149/1.3700951",

language = "English",

isbn = "9781566779586",

series = "ECS Transactions",

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pages = "179--184",

booktitle = "Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2",

edition = "6",

note = "International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting ; Conference date: 06-05-2012 Through 10-05-2012",

}

Hill, RJW, Huang, J, Loh, WY, Kim, T, Wong, MH, Veksler, D, Cunningham, TH, Droopad, R, Oh, J, Hobbs, C, Kirsch, PD & Jammy, R 2012, Integration challenges of III-V materials in advanced CMOS logic. in Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2. 6 edn, ECS Transactions, no. 6, vol. 45, Electrochemical Society Inc., pp. 179-184, International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting, Seattle, WA, United States, 6/05/12. https://doi.org/10.1149/1.3700951

Integration challenges of III-V materials in advanced CMOS logic. / Hill, R. J.W.; Huang, J.; Loh, W. Y. et al.
Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2. 6. ed. Electrochemical Society Inc., 2012. p. 179-184 (ECS Transactions; Vol. 45, No. 6).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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AU - Wong, M. H.

AU - Veksler, D.

AU - Cunningham, T. H.

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AU - Kirsch, P. D.

AU - Jammy, R.

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AB - The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.

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BT - Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2

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Y2 - 6 May 2012 through 10 May 2012

ER -

Integration challenges of III-V materials in advanced CMOS logic

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