Leakage current starved domino logic

A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in idle domino logic circuits. In the sleep mode, the output inverter and keeper transistor of a domino gate are disconnected from the power supply by turning off a high threshold voltage sleep switch. The dynamic and output nodes are discharged by the initially high subthreshold and gate oxide leakage currents produced by the NMOS transistors in the pull-down network, output inverter, and fan-out gates. After the node voltages settle, the circuit is placed into a low subthreshold and gate oxide leakage state. The effectiveness of the circuit technique for suppressing leakage current is verified under significant fluctuations of channel length, gate oxide thickness, and channel doping concentration due to process variations. The proposed circuit technique lowers the total leakage power by 67.7% to 98.8% as compared to standard dual threshold voltage domino logic circuits. Similarly, an 11.7% to 84.1% reduction in total leakage power is observed as compared to a previous sleep switch scheme in a 45nm CMOS technology.