@inproceedings{e1fe712b138e4b23a8ba2f2facff82c8,
title = "Low complexity flexible hardware efficient decimation selector",
abstract = "Coefficient decimation (CD) is a computationally efficient reconfigurable finite impulse response (FIR) filter method. Reconfigurability is achieved by decimating the fixed coefficient modal (prototype) filter in-order to realize variable bandwidth responses. Reconfigurable decimation selector is a vital part of the CD architecture which allows the user to select different decimation factor of choice. In this paper, we propose a low complexity, efficient hardware architecture for reconfigurable decimation selector. The implementation results in Virtex IV-xc4vsx35-10ff668 FPGA shows that when compared to other decimation selector techniques available in literature, the proposed implementation technique saves up to 5.2\% of area and 7.6\% of power for a filter order of 101.",
keywords = "Coefficent decimation, Lookup table, Multiplexers",
author = "V. Rakesh and Smitha, \{K. G.\} and Vinod, \{A. P.\}",
year = "2011",
doi = "10.1109/ISED.2011.18",
language = "English",
isbn = "9780769545707",
series = "Proceedings - 2011 International Symposium on Electronic System Design, ISED 2011",
pages = "77--81",
booktitle = "Proceedings - 2011 International Symposium on Electronic System Design, ISED 2011",
note = "2nd Annual International Symposium on Electronics System Design, ISED 2011 ; Conference date: 19-12-2011 Through 21-12-2011",
}