Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO

Syed Mohsin Abbas; Chi Ying Tsui

doi:10.1109/VLSI-SoC.2016.7753561

Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO

Syed Mohsin Abbas, Chi Ying Tsui

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

13 Citations (Scopus)

Abstract

This work presents a high-throughput and low-latency Index Terms-matrix inversion design for a linear pre-coder for massive MIMO systems. Because of the large number of Base Station (BS) antennas as well as the multiple User Terminals (UTs) served in a massive MIMO system, the channel matrix dimensions become larger. Inversions of such large matrices using direct inversion methods, such as used in linear pre-coders like Zero Forcing (ZF), would entail prohibitive complexity. For avoiding such complexity, Neumann series based approximate inversion has been suggested for linear pre-coders in massive MIMO systems. However the performance, complexity and convergence speed of the Neumann series approach depends very much on the initial approximation of the inverse used as a starting point. In this work, we present a novel initial approximation for the Neumann series which facilitates the parallel computation of the inverse and hence results in lower latency for inversion as well as better accuracy when compared to the previous approaches. A VLSI architecture of the proposed method is implemented for the inversion of a 16 × 16 matrix, in TSMC 65nm technology. A throughput of 0.54M to 15M matrix inversion per sec is achieved at a clock frequency of 460MHz with a 117K gate count.

Original language	English
Title of host publication	2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509035618
DOIs	https://doi.org/10.1109/VLSI-SoC.2016.7753561
Publication status	Published - 22 Nov 2016
Event	24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 - Tallinn, Estonia Duration: 26 Sept 2016 → 28 Sept 2016

Publication series

Name	2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

Conference

Conference	24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Country/Territory	Estonia
City	Tallinn
Period	26/09/16 → 28/09/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

Base Station (BS)
Massive MIMO
Matrix Inversion
Neumann Series
Zero Forcing (ZF) pre-coder

Access to Document

10.1109/VLSI-SoC.2016.7753561

Cite this

Abbas, S. M., & Tsui, C. Y. (2016). Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. In 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 Article 7753561 (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-SoC.2016.7753561

Abbas, Syed Mohsin ; Tsui, Chi Ying. / Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

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abstract = "This work presents a high-throughput and low-latency Index Terms-matrix inversion design for a linear pre-coder for massive MIMO systems. Because of the large number of Base Station (BS) antennas as well as the multiple User Terminals (UTs) served in a massive MIMO system, the channel matrix dimensions become larger. Inversions of such large matrices using direct inversion methods, such as used in linear pre-coders like Zero Forcing (ZF), would entail prohibitive complexity. For avoiding such complexity, Neumann series based approximate inversion has been suggested for linear pre-coders in massive MIMO systems. However the performance, complexity and convergence speed of the Neumann series approach depends very much on the initial approximation of the inverse used as a starting point. In this work, we present a novel initial approximation for the Neumann series which facilitates the parallel computation of the inverse and hence results in lower latency for inversion as well as better accuracy when compared to the previous approaches. A VLSI architecture of the proposed method is implemented for the inversion of a 16 × 16 matrix, in TSMC 65nm technology. A throughput of 0.54M to 15M matrix inversion per sec is achieved at a clock frequency of 460MHz with a 117K gate count.",

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Abbas, SM & Tsui, CY 2016, Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. in 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016., 7753561, 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Institute of Electrical and Electronics Engineers Inc., 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, 26/09/16. https://doi.org/10.1109/VLSI-SoC.2016.7753561

Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. / Abbas, Syed Mohsin; Tsui, Chi Ying.
2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7753561 (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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T1 - Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO

AU - Abbas, Syed Mohsin

AU - Tsui, Chi Ying

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N2 - This work presents a high-throughput and low-latency Index Terms-matrix inversion design for a linear pre-coder for massive MIMO systems. Because of the large number of Base Station (BS) antennas as well as the multiple User Terminals (UTs) served in a massive MIMO system, the channel matrix dimensions become larger. Inversions of such large matrices using direct inversion methods, such as used in linear pre-coders like Zero Forcing (ZF), would entail prohibitive complexity. For avoiding such complexity, Neumann series based approximate inversion has been suggested for linear pre-coders in massive MIMO systems. However the performance, complexity and convergence speed of the Neumann series approach depends very much on the initial approximation of the inverse used as a starting point. In this work, we present a novel initial approximation for the Neumann series which facilitates the parallel computation of the inverse and hence results in lower latency for inversion as well as better accuracy when compared to the previous approaches. A VLSI architecture of the proposed method is implemented for the inversion of a 16 × 16 matrix, in TSMC 65nm technology. A throughput of 0.54M to 15M matrix inversion per sec is achieved at a clock frequency of 460MHz with a 117K gate count.

AB - This work presents a high-throughput and low-latency Index Terms-matrix inversion design for a linear pre-coder for massive MIMO systems. Because of the large number of Base Station (BS) antennas as well as the multiple User Terminals (UTs) served in a massive MIMO system, the channel matrix dimensions become larger. Inversions of such large matrices using direct inversion methods, such as used in linear pre-coders like Zero Forcing (ZF), would entail prohibitive complexity. For avoiding such complexity, Neumann series based approximate inversion has been suggested for linear pre-coders in massive MIMO systems. However the performance, complexity and convergence speed of the Neumann series approach depends very much on the initial approximation of the inverse used as a starting point. In this work, we present a novel initial approximation for the Neumann series which facilitates the parallel computation of the inverse and hence results in lower latency for inversion as well as better accuracy when compared to the previous approaches. A VLSI architecture of the proposed method is implemented for the inversion of a 16 × 16 matrix, in TSMC 65nm technology. A throughput of 0.54M to 15M matrix inversion per sec is achieved at a clock frequency of 460MHz with a 117K gate count.

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KW - Massive MIMO

KW - Matrix Inversion

KW - Neumann Series

KW - Zero Forcing (ZF) pre-coder

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DO - 10.1109/VLSI-SoC.2016.7753561

M3 - Conference Paper published in a book

T3 - 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

BT - 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016

Y2 - 26 September 2016 through 28 September 2016

ER -

Abbas SM, Tsui CY. Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. In 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7753561. (2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016). doi: 10.1109/VLSI-SoC.2016.7753561

Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO

Abstract

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Keywords

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