LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation

Jingyang Zhu; Zhiliang Qian; Chi Ying Tsui

doi:10.1109/ASPDAC.2016.7428074

LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation

Jingyang Zhu, Zhiliang Qian, Chi Ying Tsui

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

15 Citations (Scopus)

Abstract

In this work, we propose an energy-efficient hardware accelerator for Deep Neural Network (DNN) using Low Rank Approximation (LRADNN). Using this scheme, inactive neurons in each layer of the DNN are dynamically identified and the corresponding computations are then bypassed. Accordingly, both the memory accesses and the arithmetic operations associated with these inactive neurons can be saved. Therefore, compared to the architectures using the direct feed-forward algorithm, LRADNN can achieve a higher throughput as well as a lower energy consumption with negligible prediction accuracy loss (within 0.1%). We implement and synthesize the proposed accelerator using TSMC 65nm technology. From the experimental results, a 31% to 53% energy reduction together with a 22% to 43% throughput increase can be achieved.

Original language	English
Title of host publication	2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	581-586
Number of pages	6
ISBN (Electronic)	9781467395694
DOIs	https://doi.org/10.1109/ASPDAC.2016.7428074
Publication status	Published - 7 Mar 2016
Event	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao Duration: 25 Jan 2016 → 28 Jan 2016

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	25-28-January-2016

Conference

Conference	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Country/Territory	Macao
City	Macao
Period	25/01/16 → 28/01/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/ASPDAC.2016.7428074

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Zhu, J., Qian, Z., & Tsui, C. Y. (2016). LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (pp. 581-586). Article 7428074 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7428074

Zhu, Jingyang ; Qian, Zhiliang ; Tsui, Chi Ying. / LRADNN : High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 581-586 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{f528818cedaa479799fe0fe7cd7abebd,

title = "LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation",

abstract = "In this work, we propose an energy-efficient hardware accelerator for Deep Neural Network (DNN) using Low Rank Approximation (LRADNN). Using this scheme, inactive neurons in each layer of the DNN are dynamically identified and the corresponding computations are then bypassed. Accordingly, both the memory accesses and the arithmetic operations associated with these inactive neurons can be saved. Therefore, compared to the architectures using the direct feed-forward algorithm, LRADNN can achieve a higher throughput as well as a lower energy consumption with negligible prediction accuracy loss (within 0.1\%). We implement and synthesize the proposed accelerator using TSMC 65nm technology. From the experimental results, a 31\% to 53\% energy reduction together with a 22\% to 43\% throughput increase can be achieved.",

author = "Jingyang Zhu and Zhiliang Qian and Tsui, \{Chi Ying\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 ; Conference date: 25-01-2016 Through 28-01-2016",

year = "2016",

month = mar,

day = "7",

doi = "10.1109/ASPDAC.2016.7428074",

language = "English",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "581--586",

booktitle = "2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016",

}

Zhu, J, Qian, Z & Tsui, CY 2016, LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. in 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016., 7428074, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 25-28-January-2016, Institute of Electrical and Electronics Engineers Inc., pp. 581-586, 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, 25/01/16. https://doi.org/10.1109/ASPDAC.2016.7428074

LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. / Zhu, Jingyang; Qian, Zhiliang; Tsui, Chi Ying.
2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 581-586 7428074 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - LRADNN

T2 - 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016

AU - Zhu, Jingyang

AU - Qian, Zhiliang

AU - Tsui, Chi Ying

PY - 2016/3/7

Y1 - 2016/3/7

N2 - In this work, we propose an energy-efficient hardware accelerator for Deep Neural Network (DNN) using Low Rank Approximation (LRADNN). Using this scheme, inactive neurons in each layer of the DNN are dynamically identified and the corresponding computations are then bypassed. Accordingly, both the memory accesses and the arithmetic operations associated with these inactive neurons can be saved. Therefore, compared to the architectures using the direct feed-forward algorithm, LRADNN can achieve a higher throughput as well as a lower energy consumption with negligible prediction accuracy loss (within 0.1%). We implement and synthesize the proposed accelerator using TSMC 65nm technology. From the experimental results, a 31% to 53% energy reduction together with a 22% to 43% throughput increase can be achieved.

AB - In this work, we propose an energy-efficient hardware accelerator for Deep Neural Network (DNN) using Low Rank Approximation (LRADNN). Using this scheme, inactive neurons in each layer of the DNN are dynamically identified and the corresponding computations are then bypassed. Accordingly, both the memory accesses and the arithmetic operations associated with these inactive neurons can be saved. Therefore, compared to the architectures using the direct feed-forward algorithm, LRADNN can achieve a higher throughput as well as a lower energy consumption with negligible prediction accuracy loss (within 0.1%). We implement and synthesize the proposed accelerator using TSMC 65nm technology. From the experimental results, a 31% to 53% energy reduction together with a 22% to 43% throughput increase can be achieved.

UR - https://openalex.org/W2294023757

UR - https://www.scopus.com/pages/publications/84996772852

U2 - 10.1109/ASPDAC.2016.7428074

DO - 10.1109/ASPDAC.2016.7428074

M3 - Conference Paper published in a book

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 581

EP - 586

BT - 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 25 January 2016 through 28 January 2016

ER -

Zhu J, Qian Z, Tsui CY. LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 581-586. 7428074. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2016.7428074

LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation

Abstract

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