Matching the Speed Gap between SRAM and DRAM

With the constantly increasing Internet traffic, buffers are becoming major bottlenecks for today's high-end routers. In particular, router buffers are required to have both high speed and large capacities, which are hard to build with current single memory technology, such as SRAM or DRAM. A general approach is to make a combination of the SRAM and DRAM and exploit advantages from both. The main obstacle is to find a way matching the speed gap between them. And the requirement to maintain multiple flows in the system further complicates the problem. In this paper, we first investigate previous solutions that use different access granularities to match the speed gap. We point out their intrinsic scaling problems when the number of flows increases. Then, we propose to use parallelism to match the speed gap. Numerical studies and simulations both show that our proposal can theoretically support any number of flows in the router with just little SRAM under practical traffic. In addition, the memory management algorithm is also more scalable compared to those in previous solutions.