Methodologies for layout decomposition and mask optimization: A systematic review

Yuzhe Ma; Xuan Zeng; Bei Yu

doi:10.1109/VLSI-SoC.2017.8203477

Methodologies for layout decomposition and mask optimization: A systematic review

Yuzhe Ma, Xuan Zeng, Bei Yu

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

10 Citations (Scopus)

Abstract

As the transistor feature size keeps shrinking, manufacturability has become an urgent issue in semiconductor industry. In order to improve the manufacturability, various resolution enhancement techniques have been proposed, among which layout decomposition and mask optimization have been considered as the most powerful solutions in advanced technology nodes. Different from many previous survey papers that categorize literatures by type of manufacturing process, we argue that different manufacturing scenarios can share similar mathematical models. This paper carefully summarizes a series of methodologies that have been successfully applied to VLSI layout decomposition and mask optimization problems.

Original language	English
Title of host publication	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
Publisher	IEEE Computer Society
ISBN (Electronic)	9781538628805
DOIs	https://doi.org/10.1109/VLSI-SoC.2017.8203477
Publication status	Published - 13 Dec 2017
Externally published	Yes
Event	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates Duration: 23 Oct 2017 → 25 Oct 2017

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	23/10/17 → 25/10/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/VLSI-SoC.2017.8203477

Cite this

Ma, Y., Zeng, X., & Yu, B. (2017). Methodologies for layout decomposition and mask optimization: A systematic review. In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings Article 8203477 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2017.8203477

@inproceedings{4643ac343b054721a432709ff484099c,

title = "Methodologies for layout decomposition and mask optimization: A systematic review",

abstract = "As the transistor feature size keeps shrinking, manufacturability has become an urgent issue in semiconductor industry. In order to improve the manufacturability, various resolution enhancement techniques have been proposed, among which layout decomposition and mask optimization have been considered as the most powerful solutions in advanced technology nodes. Different from many previous survey papers that categorize literatures by type of manufacturing process, we argue that different manufacturing scenarios can share similar mathematical models. This paper carefully summarizes a series of methodologies that have been successfully applied to VLSI layout decomposition and mask optimization problems.",

author = "Yuzhe Ma and Xuan Zeng and Bei Yu",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 ; Conference date: 23-10-2017 Through 25-10-2017",

year = "2017",

month = dec,

day = "13",

doi = "10.1109/VLSI-SoC.2017.8203477",

language = "English",

series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",

publisher = "IEEE Computer Society",

booktitle = "25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings",

}

Ma, Y, Zeng, X & Yu, B 2017, Methodologies for layout decomposition and mask optimization: A systematic review. in 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings., 8203477, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, 23/10/17. https://doi.org/10.1109/VLSI-SoC.2017.8203477

Methodologies for layout decomposition and mask optimization: A systematic review. / Ma, Yuzhe; Zeng, Xuan; Yu, Bei.
25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 2017. 8203477 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - Methodologies for layout decomposition and mask optimization

T2 - 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017

AU - Ma, Yuzhe

AU - Zeng, Xuan

AU - Yu, Bei

PY - 2017/12/13

Y1 - 2017/12/13

N2 - As the transistor feature size keeps shrinking, manufacturability has become an urgent issue in semiconductor industry. In order to improve the manufacturability, various resolution enhancement techniques have been proposed, among which layout decomposition and mask optimization have been considered as the most powerful solutions in advanced technology nodes. Different from many previous survey papers that categorize literatures by type of manufacturing process, we argue that different manufacturing scenarios can share similar mathematical models. This paper carefully summarizes a series of methodologies that have been successfully applied to VLSI layout decomposition and mask optimization problems.

AB - As the transistor feature size keeps shrinking, manufacturability has become an urgent issue in semiconductor industry. In order to improve the manufacturability, various resolution enhancement techniques have been proposed, among which layout decomposition and mask optimization have been considered as the most powerful solutions in advanced technology nodes. Different from many previous survey papers that categorize literatures by type of manufacturing process, we argue that different manufacturing scenarios can share similar mathematical models. This paper carefully summarizes a series of methodologies that have been successfully applied to VLSI layout decomposition and mask optimization problems.

UR - https://www.scopus.com/pages/publications/85058484189

U2 - 10.1109/VLSI-SoC.2017.8203477

DO - 10.1109/VLSI-SoC.2017.8203477

M3 - Conference Paper published in a book

AN - SCOPUS:85058484189

T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

BT - 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings

PB - IEEE Computer Society

Y2 - 23 October 2017 through 25 October 2017

ER -

Methodologies for layout decomposition and mask optimization: A systematic review

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