Model reduction for PEEC models including retardation

J. Cullum; A. E. Ruehli; T. Zhang

doi:10.1109/EPEP.1998.734055

Model reduction for PEEC models including retardation

J. Cullum^*, A. E. Ruehli, T. Zhang

^*Corresponding author for this work

Research output: Contribution to conference › Conference Paper › peer-review

12 Citations (Scopus)

Abstract

Partial Element Equivalent Circuits (PEEC) are applied by many for modeling interconnects in packages. These models are suitable for a wide range of three-dimensional problems. When PEEC models are applied to large packages, large equivalent circuits are generated. Model reduction techniques for PEEC models have been proposed by several researchers but typically for problems where retardation is not important or where two-dimensional models suffice. In this paper we give a new model reduction procedure applicable to full wave PEEC models which include losses and retardation. We include two examples to demonstrate the application of this method.

Original language	English
Pages	287-290
Number of pages	4
DOIs	https://doi.org/10.1109/EPEP.1998.734055
Publication status	Published - 1998
Externally published	Yes
Event	Proceedings of the 1998 IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging - West Point, NY, USA Duration: 26 Oct 1998 → 28 Oct 1998

Conference

Conference	Proceedings of the 1998 IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging
City	West Point, NY, USA
Period	26/10/98 → 28/10/98

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10.1109/EPEP.1998.734055

Cite this

@conference{e5322b1f162d4cb8955eb3707670593f,

title = "Model reduction for PEEC models including retardation",

abstract = "Partial Element Equivalent Circuits (PEEC) are applied by many for modeling interconnects in packages. These models are suitable for a wide range of three-dimensional problems. When PEEC models are applied to large packages, large equivalent circuits are generated. Model reduction techniques for PEEC models have been proposed by several researchers but typically for problems where retardation is not important or where two-dimensional models suffice. In this paper we give a new model reduction procedure applicable to full wave PEEC models which include losses and retardation. We include two examples to demonstrate the application of this method.",

author = "J. Cullum and Ruehli, \{A. E.\} and T. Zhang",

year = "1998",

doi = "10.1109/EPEP.1998.734055",

language = "English",

pages = "287--290",

note = "Proceedings of the 1998 IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging ; Conference date: 26-10-1998 Through 28-10-1998",

}

TY - CONF

T1 - Model reduction for PEEC models including retardation

AU - Cullum, J.

AU - Ruehli, A. E.

AU - Zhang, T.

PY - 1998

Y1 - 1998

N2 - Partial Element Equivalent Circuits (PEEC) are applied by many for modeling interconnects in packages. These models are suitable for a wide range of three-dimensional problems. When PEEC models are applied to large packages, large equivalent circuits are generated. Model reduction techniques for PEEC models have been proposed by several researchers but typically for problems where retardation is not important or where two-dimensional models suffice. In this paper we give a new model reduction procedure applicable to full wave PEEC models which include losses and retardation. We include two examples to demonstrate the application of this method.

AB - Partial Element Equivalent Circuits (PEEC) are applied by many for modeling interconnects in packages. These models are suitable for a wide range of three-dimensional problems. When PEEC models are applied to large packages, large equivalent circuits are generated. Model reduction techniques for PEEC models have been proposed by several researchers but typically for problems where retardation is not important or where two-dimensional models suffice. In this paper we give a new model reduction procedure applicable to full wave PEEC models which include losses and retardation. We include two examples to demonstrate the application of this method.

UR - https://www.webofscience.com/wos/woscc/full-record/WOS:000078238300065

UR - https://openalex.org/W1927547807

UR - https://www.scopus.com/pages/publications/0032293671

U2 - 10.1109/EPEP.1998.734055

DO - 10.1109/EPEP.1998.734055

M3 - Conference Paper

SP - 287

EP - 290

T2 - Proceedings of the 1998 IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging

Y2 - 26 October 1998 through 28 October 1998

ER -

Model reduction for PEEC models including retardation

Abstract

Conference

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