Modeling the substrate depletion region for GaAs FETs fabricated on semi-insulating substrates

Peter George; Ping K. Ko; Chenming Hu

doi:10.1016/0038-1101(89)90184-6

Modeling the substrate depletion region for GaAs FETs fabricated on semi-insulating substrates

Peter George^*, Ping K. Ko, Chenming Hu

^*Corresponding author for this work

Research output: Contribution to journal › Journal Article › peer-review

1 Citation (Scopus)

Abstract

A calculation of the channel-substrate space charge densities and dimensions is required in the formulation of device models for modern GaAs FETs which are fabricated on semi-insulating substrates with multiple deep levels. We describe a procedure to deduce this information from the compensation scheme utilized to obtain semi-insulating behavior.

Original language	English
Pages (from-to)	165-168
Number of pages	4
Journal	Solid-State Electronics
Volume	32
Issue number	2
DOIs	https://doi.org/10.1016/0038-1101(89)90184-6
Publication status	Published - Feb 1989
Externally published	Yes

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title = "Modeling the substrate depletion region for GaAs FETs fabricated on semi-insulating substrates",

abstract = "A calculation of the channel-substrate space charge densities and dimensions is required in the formulation of device models for modern GaAs FETs which are fabricated on semi-insulating substrates with multiple deep levels. We describe a procedure to deduce this information from the compensation scheme utilized to obtain semi-insulating behavior.",

author = "Peter George and Ko, \{Ping K.\} and Chenming Hu",

year = "1989",

month = feb,

doi = "10.1016/0038-1101(89)90184-6",

language = "English",

volume = "32",

pages = "165--168",

journal = "Solid-State Electronics",

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T1 - Modeling the substrate depletion region for GaAs FETs fabricated on semi-insulating substrates

AU - George, Peter

AU - Ko, Ping K.

AU - Hu, Chenming

PY - 1989/2

Y1 - 1989/2

N2 - A calculation of the channel-substrate space charge densities and dimensions is required in the formulation of device models for modern GaAs FETs which are fabricated on semi-insulating substrates with multiple deep levels. We describe a procedure to deduce this information from the compensation scheme utilized to obtain semi-insulating behavior.

AB - A calculation of the channel-substrate space charge densities and dimensions is required in the formulation of device models for modern GaAs FETs which are fabricated on semi-insulating substrates with multiple deep levels. We describe a procedure to deduce this information from the compensation scheme utilized to obtain semi-insulating behavior.

UR - https://www.webofscience.com/wos/woscc/full-record/WOS:A1989T446900011

UR - https://www.scopus.com/pages/publications/0024612529

U2 - 10.1016/0038-1101(89)90184-6

DO - 10.1016/0038-1101(89)90184-6

M3 - Journal Article

AN - SCOPUS:0024612529

SN - 0038-1101

VL - 32

SP - 165

EP - 168

JO - Solid-State Electronics

JF - Solid-State Electronics

IS - 2

ER -

Modeling the substrate depletion region for GaAs FETs fabricated on semi-insulating substrates

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