Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy

Saeed Shamshiri*, Kwang Ting Cheng

*Corresponding author for this work

Research output: Chapter in Book/Conference Proceeding/ReportConference Paper published in a bookpeer-review

8 Citations (Scopus)

Abstract

In this paper, we propose a quality metric for an NoC and model the yield and cost of a spare-enhanced multicore chip subject to a given quality constraint. Our experiments show that the overall quality of a mesh-based NoC depends more on the reliability of the inner links than the outer links; therefore, a non-uniform distribution of spare wires could be more effective and cost efficient than a uniform approach.

Original languageEnglish
Title of host publicationProceedings - 28th IEEE VLSI Test Symposium, VTS10
Pages194-199
Number of pages6
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event28th IEEE VLSI Test Symposium, VTS10 - Santa Cruz, CA, United States
Duration: 19 Apr 201022 Apr 2010

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference28th IEEE VLSI Test Symposium, VTS10
Country/TerritoryUnited States
CitySanta Cruz, CA
Period19/04/1022/04/10

Keywords

  • NoC
  • Non-uniform spare distributtion
  • Quality analysis
  • SoC
  • Yield and cost modeling

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