Monolithic DC-DC converter analysis and MOSFET gate voltage optimization

Volkan Kursun; Siva G. Narendra; Vivek K. De; Eby G. Friedman

doi:10.1109/ISQED.2003.1194746

Monolithic DC-DC converter analysis and MOSFET gate voltage optimization

Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

42 Citations (Scopus)

Abstract

The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 μm CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5%, improving the efficiency by 3.9% as compared to a full swing DC-DC converter.

Original language	English
Title of host publication	Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003
Publisher	IEEE Computer Society
Pages	279-284
Number of pages	6
ISBN (Electronic)	0769518818
DOIs	https://doi.org/10.1109/ISQED.2003.1194746
Publication status	Published - 2003
Externally published	Yes
Event	2003 4th International Symposium on Quality Electronic Design, ISQED 2003 - San Jose, United States Duration: 24 Mar 2003 → 26 Mar 2003

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2003-January
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	2003 4th International Symposium on Quality Electronic Design, ISQED 2003
Country/Territory	United States
City	San Jose
Period	24/03/03 → 26/03/03

Bibliographical note

Publisher Copyright:
© 2003 IEEE.

Keywords

Buck converters
CMOS technology
DC-DC power converters
Impedance
MOSFET circuits
Power MOSFET
Semiconductor device modeling
Space technology
Switching frequency
Voltage

Access to Document

10.1109/ISQED.2003.1194746

Cite this

Kursun, V., Narendra, S. G., De, V. K., & Friedman, E. G. (2003). Monolithic DC-DC converter analysis and MOSFET gate voltage optimization. In Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003 (pp. 279-284). Article 1194746 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2003-January). IEEE Computer Society. https://doi.org/10.1109/ISQED.2003.1194746

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title = "Monolithic DC-DC converter analysis and MOSFET gate voltage optimization",

abstract = "The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 μm CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88\% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5\%, improving the efficiency by 3.9\% as compared to a full swing DC-DC converter.",

keywords = "Buck converters, CMOS technology, DC-DC power converters, Impedance, MOSFET circuits, Power MOSFET, Semiconductor device modeling, Space technology, Switching frequency, Voltage",

author = "Volkan Kursun and Narendra, \{Siva G.\} and De, \{Vivek K.\} and Friedman, \{Eby G.\}",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 4th International Symposium on Quality Electronic Design, ISQED 2003 ; Conference date: 24-03-2003 Through 26-03-2003",

year = "2003",

doi = "10.1109/ISQED.2003.1194746",

language = "English",

series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

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Kursun, V, Narendra, SG, De, VK & Friedman, EG 2003, Monolithic DC-DC converter analysis and MOSFET gate voltage optimization. in Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003., 1194746, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2003-January, IEEE Computer Society, pp. 279-284, 2003 4th International Symposium on Quality Electronic Design, ISQED 2003, San Jose, United States, 24/03/03. https://doi.org/10.1109/ISQED.2003.1194746

Monolithic DC-DC converter analysis and MOSFET gate voltage optimization. / Kursun, Volkan; Narendra, Siva G.; De, Vivek K. et al.
Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003. IEEE Computer Society, 2003. p. 279-284 1194746 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2003-January).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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AU - Kursun, Volkan

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PY - 2003

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N2 - The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 μm CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5%, improving the efficiency by 3.9% as compared to a full swing DC-DC converter.

AB - The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 μm CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5%, improving the efficiency by 3.9% as compared to a full swing DC-DC converter.

KW - Buck converters

KW - CMOS technology

KW - DC-DC power converters

KW - Impedance

KW - MOSFET circuits

KW - Power MOSFET

KW - Semiconductor device modeling

KW - Space technology

KW - Switching frequency

KW - Voltage

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BT - Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003

PB - IEEE Computer Society

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ER -

Kursun V, Narendra SG, De VK, Friedman EG. Monolithic DC-DC converter analysis and MOSFET gate voltage optimization. In Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003. IEEE Computer Society. 2003. p. 279-284. 1194746. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2003.1194746

Monolithic DC-DC converter analysis and MOSFET gate voltage optimization

Abstract

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Bibliographical note

Keywords

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