TY - JOUR
T1 - Multikernel data partitioning with channel on OpenCL-based FPGAs
AU - Wang, Zeke
AU - Paul, Johns
AU - He, Bingsheng
AU - Zhang, Wei
PY - 2017/6
Y1 - 2017/6
N2 - Recently, field-programmable gate array (FPGA) vendors (such as Altera) have started to address the programmability issues of FPGAS via OpenCL SDKs. In this paper, we analyze the performance of relational database applications on FPGAS using OpenCL. In particular, we study how to improve the performance of data partitioning, which is a very important building block in relational database. Since the data partitioning causes random memory accesses, it is time-consuming, and then, it has been the major bottleneck for database operators, such as partitioned hash join. In particular, we import the state-of-theart OpenCL implementation of data partitioning from OmniDB, which was originally designed and optimized for CPUs/GPUs, and we find that this implementation suffers from both lock overhead and memory bandwidth overhead. Accordingly, we present a multikernel approach to address the lock overhead by leveraging two emerging features (task kernel and channel) from Altera OpenCL software development kit. In order to reduce the memory bandwidth overhead, on-chip buckets are used to reduce the number of random global memory transactions. We further develop an FPGA-specific cost model to guide the parameter configuration. We evaluate the proposed design on a recent OpenCL-based FPGA. We have applied our optimized partitioning method to a number of data processing tasks, including hash join, histogram, and hash search. Our experimental results demonstrate that our cost model can accurately guide the user to determine the optimal parameter combination for data partitioning and the optimal parameter combination can achieve 16.6× speedup over the default multithreaded implementation. 2017 IEEE.
AB - Recently, field-programmable gate array (FPGA) vendors (such as Altera) have started to address the programmability issues of FPGAS via OpenCL SDKs. In this paper, we analyze the performance of relational database applications on FPGAS using OpenCL. In particular, we study how to improve the performance of data partitioning, which is a very important building block in relational database. Since the data partitioning causes random memory accesses, it is time-consuming, and then, it has been the major bottleneck for database operators, such as partitioned hash join. In particular, we import the state-of-theart OpenCL implementation of data partitioning from OmniDB, which was originally designed and optimized for CPUs/GPUs, and we find that this implementation suffers from both lock overhead and memory bandwidth overhead. Accordingly, we present a multikernel approach to address the lock overhead by leveraging two emerging features (task kernel and channel) from Altera OpenCL software development kit. In order to reduce the memory bandwidth overhead, on-chip buckets are used to reduce the number of random global memory transactions. We further develop an FPGA-specific cost model to guide the parameter configuration. We evaluate the proposed design on a recent OpenCL-based FPGA. We have applied our optimized partitioning method to a number of data processing tasks, including hash join, histogram, and hash search. Our experimental results demonstrate that our cost model can accurately guide the user to determine the optimal parameter combination for data partitioning and the optimal parameter combination can achieve 16.6× speedup over the default multithreaded implementation. 2017 IEEE.
KW - Channel
KW - Data partitioning
KW - Database
KW - Fieldprogrammable gate array (FPGA)
KW - High-level synthesis
KW - OpenCL
UR - https://www.webofscience.com/wos/woscc/full-record/WOS:000402137300010
UR - https://openalex.org/W2588542619
UR - https://www.scopus.com/pages/publications/85012992059
U2 - 10.1109/TVLSI.2017.2653818
DO - 10.1109/TVLSI.2017.2653818
M3 - Journal Article
SN - 1063-8210
VL - 25
SP - 1906
EP - 1918
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 6
M1 - 7857086
ER -