@inproceedings{ca48040bfef349b497996de9e4ea5c57,
title = "Multiple cell upsets tolerant content-addressable memory",
abstract = "Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65 nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. It has been previously proposed that Hamming distance based approaches are good for SCUs but are not effective for MCUs. These schemes require a large number of extra parity bits for mitigating MCUs, and so they are not a practical solution for CAM devices. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85\% fewer parity bits compared to traditional Hamming distance based schemes",
keywords = "Error correcting code, MCU confinement, multiple cell upsets, parity bits, single-error correcting codes, softerror rate",
author = "Abbas, \{Syed Mohsin\} and Sanghyeon Baeg and Sungju Park",
year = "2011",
language = "English",
isbn = "9781424491117",
series = "IEEE International Reliability Physics Symposium Proceedings",
pages = "SE.1.1--SE.1.5",
booktitle = "2011 International Reliability Physics Symposium, IRPS 2011",
note = "49th International Reliability Physics Symposium, IRPS 2011 ; Conference date: 10-04-2011 Through 14-04-2011",
}