NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Matthew Poremba; Tao Zhang; Yuan Xie

doi:10.1109/LCA.2015.2402435

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Matthew Poremba^*, Tao Zhang, Yuan Xie

^*Corresponding author for this work

Research output: Contribution to journal › Journal Article › peer-review

204 Citations (Scopus)

Abstract

In this letter, a flexible memory simulator - NVMain 2.0, is introduced to help the community for modeling not only commodity DRAMs but also emerging memory technologies, such as die-stacked DRAM caches, non-volatile memories (e.g., STT-RAM, PCRAM, and ReRAM) including multi-level cells (MLC), and hybrid non-volatile plus DRAM memory systems. Compared to existing memory simulators, NVMain 2.0 features a flexible user interface with compelling simulation speed and the capability of providing sub-array-level parallelism, fine-grained refresh, MLC and data encoder modeling, and distributed energy profiling.

Original language	English
Article number	7038174
Pages (from-to)	140-143
Number of pages	4
Journal	IEEE Computer Architecture Letters
Volume	14
Issue number	2
DOIs	https://doi.org/10.1109/LCA.2015.2402435
Publication status	Published - 1 Jul 2015
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

Memory architecture
SDRAM
nonvolatile memory
phase change memory
random access memory

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10.1109/LCA.2015.2402435

Cite this

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title = "NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems",

abstract = "In this letter, a flexible memory simulator - NVMain 2.0, is introduced to help the community for modeling not only commodity DRAMs but also emerging memory technologies, such as die-stacked DRAM caches, non-volatile memories (e.g., STT-RAM, PCRAM, and ReRAM) including multi-level cells (MLC), and hybrid non-volatile plus DRAM memory systems. Compared to existing memory simulators, NVMain 2.0 features a flexible user interface with compelling simulation speed and the capability of providing sub-array-level parallelism, fine-grained refresh, MLC and data encoder modeling, and distributed energy profiling.",

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author = "Matthew Poremba and Tao Zhang and Yuan Xie",

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year = "2015",

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T2 - A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

AU - Poremba, Matthew

AU - Zhang, Tao

AU - Xie, Yuan

PY - 2015/7/1

Y1 - 2015/7/1

N2 - In this letter, a flexible memory simulator - NVMain 2.0, is introduced to help the community for modeling not only commodity DRAMs but also emerging memory technologies, such as die-stacked DRAM caches, non-volatile memories (e.g., STT-RAM, PCRAM, and ReRAM) including multi-level cells (MLC), and hybrid non-volatile plus DRAM memory systems. Compared to existing memory simulators, NVMain 2.0 features a flexible user interface with compelling simulation speed and the capability of providing sub-array-level parallelism, fine-grained refresh, MLC and data encoder modeling, and distributed energy profiling.

AB - In this letter, a flexible memory simulator - NVMain 2.0, is introduced to help the community for modeling not only commodity DRAMs but also emerging memory technologies, such as die-stacked DRAM caches, non-volatile memories (e.g., STT-RAM, PCRAM, and ReRAM) including multi-level cells (MLC), and hybrid non-volatile plus DRAM memory systems. Compared to existing memory simulators, NVMain 2.0 features a flexible user interface with compelling simulation speed and the capability of providing sub-array-level parallelism, fine-grained refresh, MLC and data encoder modeling, and distributed energy profiling.

KW - Memory architecture

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KW - nonvolatile memory

KW - phase change memory

KW - random access memory

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DO - 10.1109/LCA.2015.2402435

M3 - Journal Article

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EP - 143

JO - IEEE Computer Architecture Letters

JF - IEEE Computer Architecture Letters

IS - 2

M1 - 7038174

ER -

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Abstract

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Keywords

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