On error modeling of electrical bugs for post-silicon timing validation

Ming Gao; Peter Lisherness; Kwang Ting Cheng; Jing Jia Liou

doi:10.1109/ASPDAC.2012.6165046

On error modeling of electrical bugs for post-silicon timing validation

Ming Gao^*, Peter Lisherness, Kwang Ting Cheng, Jing Jia Liou

^*Corresponding author for this work

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

7 Citations (Scopus)

Abstract

There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently and with sufficient precision. Experimental results demonstrate that the proposed approach produced an error model six times more accurate than the prior art with a negligible simulation overhead.

Original language	English
Title of host publication	ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages	701-706
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2012.6165046
Publication status	Published - 2012
Externally published	Yes
Event	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia Duration: 30 Jan 2012 → 2 Feb 2012

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
Country/Territory	Australia
City	Sydney, NSW
Period	30/01/12 → 2/02/12

Access to Document

10.1109/ASPDAC.2012.6165046

Cite this

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title = "On error modeling of electrical bugs for post-silicon timing validation",

abstract = "There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently and with sufficient precision. Experimental results demonstrate that the proposed approach produced an error model six times more accurate than the prior art with a negligible simulation overhead.",

author = "Ming Gao and Peter Lisherness and Cheng, \{Kwang Ting\} and Liou, \{Jing Jia\}",

year = "2012",

doi = "10.1109/ASPDAC.2012.6165046",

language = "English",

isbn = "9781467307727",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "701--706",

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note = "17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 ; Conference date: 30-01-2012 Through 02-02-2012",

}

Gao, M, Lisherness, P, Cheng, KT & Liou, JJ 2012, On error modeling of electrical bugs for post-silicon timing validation. in ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference., 6165046, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 701-706, 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, NSW, Australia, 30/01/12. https://doi.org/10.1109/ASPDAC.2012.6165046

On error modeling of electrical bugs for post-silicon timing validation. / Gao, Ming; Lisherness, Peter; Cheng, Kwang Ting et al.
ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. 2012. p. 701-706 6165046 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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N2 - There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently and with sufficient precision. Experimental results demonstrate that the proposed approach produced an error model six times more accurate than the prior art with a negligible simulation overhead.

AB - There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently and with sufficient precision. Experimental results demonstrate that the proposed approach produced an error model six times more accurate than the prior art with a negligible simulation overhead.

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ER -

On error modeling of electrical bugs for post-silicon timing validation

Abstract

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