TY - JOUR
T1 - On-off differential current-mode circuits for Gabor-type spatial filtering
AU - Shi, Bertram E.
AU - Choi, Thomas Yu Wing
AU - Boahen, Kwabena
PY - 2002
Y1 - 2002
N2 - We describe a current-mode circuit for Gabor-type image filtering which uses a differential representation where positive (on) and negative (off) signals are encoded using separate channels. Previous current-mode implementations represented positive and negative signals as variations around a constant bias at every pixel. However, this bias current has several disadvantages. First, variations in it introduce significant additive fixed pattern noise to the output. Second, it dissipates power even with zero input. Third, if the output is encoded using the Address Representation, the bias current sets up a quiescent firing rate which loads the bus. The architecture proposed here alleviates these problems since a zero signal is encoded as nearly zero current in both channels. On the other hand, the transistor count and the address space are doubled. Measurements from a 1 by 25 pixel array with a cell size of 64um by 540um was fabricated in the AMI1.75um process available through MOSIS. Quiescent power dissipation was 5umW total.
AB - We describe a current-mode circuit for Gabor-type image filtering which uses a differential representation where positive (on) and negative (off) signals are encoded using separate channels. Previous current-mode implementations represented positive and negative signals as variations around a constant bias at every pixel. However, this bias current has several disadvantages. First, variations in it introduce significant additive fixed pattern noise to the output. Second, it dissipates power even with zero input. Third, if the output is encoded using the Address Representation, the bias current sets up a quiescent firing rate which loads the bus. The architecture proposed here alleviates these problems since a zero signal is encoded as nearly zero current in both channels. On the other hand, the transistor count and the address space are doubled. Measurements from a 1 by 25 pixel array with a cell size of 64um by 540um was fabricated in the AMI1.75um process available through MOSIS. Quiescent power dissipation was 5umW total.
UR - https://openalex.org/W1943120532
UR - https://www.scopus.com/pages/publications/0036297109
U2 - 10.1109/ISCAS.2002.1011455
DO - 10.1109/ISCAS.2002.1011455
M3 - Journal Article
SN - 0271-4310
VL - 2
SP - 724
EP - 727
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
ER -