On the body-source built-in potential lowering of SOI MOSFETs

Pin Su; Samuel K.H. Fung; Peter W. Wyatt; Hui Wan; Ali M. Niknejad; Mansun Chan; Chenming Hu

doi:10.1109/LED.2002.807696

On the body-source built-in potential lowering of SOI MOSFETs

Pin Su^*, Samuel K.H. Fung, Peter W. Wyatt, Hui Wan, Ali M. Niknejad, Mansun Chan, Chenming Hu

^*Corresponding author for this work

Department of Electronic and Computer Engineering

Research output: Contribution to journal › Journal Article › peer-review

16 Citations (Scopus)

Abstract

This letter provides a viewpoint for the characterization of state-of-the-art thin film sllicon-on-insulator (SOI) MOSFETs. Based on body - source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.

Original language	English
Pages (from-to)	90-92
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	24
Issue number	2
DOIs	https://doi.org/10.1109/LED.2002.807696
Publication status	Published - 1 Mar 2003

Keywords

Body-source built-in potential lowering
Floating-body effect
Impact ionization
SOI CMOS
Silicon-film-thickness scaling

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10.1109/LED.2002.807696

Cite this

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abstract = "This letter provides a viewpoint for the characterization of state-of-the-art thin film sllicon-on-insulator (SOI) MOSFETs. Based on body - source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.",

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AU - Su, Pin

AU - Fung, Samuel K.H.

AU - Wyatt, Peter W.

AU - Wan, Hui

AU - Niknejad, Ali M.

AU - Chan, Mansun

AU - Hu, Chenming

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AB - This letter provides a viewpoint for the characterization of state-of-the-art thin film sllicon-on-insulator (SOI) MOSFETs. Based on body - source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.

KW - Body-source built-in potential lowering

KW - Floating-body effect

KW - Impact ionization

KW - SOI CMOS

KW - Silicon-film-thickness scaling

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JF - IEEE Electron Device Letters

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On the body-source built-in potential lowering of SOI MOSFETs

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Keywords

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