Abstract
Three general sets of solutions are formulated to model an arbitrarily configured double-gate (DG) metal-oxide-semiconductor (MOS) capacitor with an undoped silicon body under general bias conditions. The "zero-field" and the "zero-potential" solutions are separated by the "zero-field and zero-potential" solution. Based on the zero-field solution, approximate expressions are proposed to explicitly relate the potential (Ψs) and the electric field (Es) on the silicon side of the oxide/silicon interface of a symmetrical DG MOS capacitor. Based on these expressions, models of the threshold voltage and the current-voltage (IV) characteristics incorporating the mobility degradation effect at high "vertical" electric field and the velocity saturation effect at high "lateral" electric field of a symmetrical DG MOS field-effect transistor are developed. Comparisons are made among the presently proposed IV model, some previously proposed IV models and numerical simulations.
| Original language | English |
|---|---|
| Pages | 692-697 |
| Number of pages | 6 |
| Publication status | Published - 2006 |
| Event | 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings - Boston, MA, United States Duration: 7 May 2006 → 11 May 2006 |
Conference
| Conference | 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings |
|---|---|
| Country/Territory | United States |
| City | Boston, MA |
| Period | 7/05/06 → 11/05/06 |
Keywords
- Current-voltage characteristics
- Double-gate MOSFET
- Modeling
- Threshold voltage
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