Optimal device architecture and hetero-integration scheme for III-V CMOS

Ze Yuan; Archana Kumar; Chien Yu Chen; Aneesh Nainani; Peter Griffin; Albert Wang; Wei Wang; Man Hoi Wong; Ravi Droopad; Rocio Contreras-Guerrero; Paul Kirsch; Raj Jammy; James Plummer; Krishna C. Saraswat

Optimal device architecture and hetero-integration scheme for III-V CMOS

Ze Yuan, Archana Kumar, Chien Yu Chen, Aneesh Nainani, Peter Griffin, Albert Wang, Wei Wang, Man Hoi Wong, Ravi Droopad, Rocio Contreras-Guerrero, Paul Kirsch, Raj Jammy, James Plummer, Krishna C. Saraswat

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

11 Citations (Scopus)

Abstract

Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon [2]. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.

Original language	English
Title of host publication	2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers
Pages	T54-T55
Publication status	Published - 2013
Externally published	Yes
Event	2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan Duration: 11 Jun 2013 → 13 Jun 2013

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	2013 Symposium on VLSI Technology, VLSIT 2013
Country/Territory	Japan
City	Kyoto
Period	11/06/13 → 13/06/13

Cite this

Yuan, Z., Kumar, A., Chen, C. Y., Nainani, A., Griffin, P., Wang, A., Wang, W., Wong, M. H., Droopad, R., Contreras-Guerrero, R., Kirsch, P., Jammy, R., Plummer, J., & Saraswat, K. C. (2013). Optimal device architecture and hetero-integration scheme for III-V CMOS. In 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers (pp. T54-T55). Article 6576683 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{62bbe490533545bd8b20d1937ec17783,

title = "Optimal device architecture and hetero-integration scheme for III-V CMOS",

abstract = "Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon [2]. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.",

author = "Ze Yuan and Archana Kumar and Chen, \{Chien Yu\} and Aneesh Nainani and Peter Griffin and Albert Wang and Wei Wang and Wong, \{Man Hoi\} and Ravi Droopad and Rocio Contreras-Guerrero and Paul Kirsch and Raj Jammy and James Plummer and Saraswat, \{Krishna C.\}",

year = "2013",

language = "English",

isbn = "9784863483477",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "T54--T55",

booktitle = "2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers",

note = "2013 Symposium on VLSI Technology, VLSIT 2013 ; Conference date: 11-06-2013 Through 13-06-2013",

}

Yuan, Z, Kumar, A, Chen, CY, Nainani, A, Griffin, P, Wang, A, Wang, W, Wong, MH, Droopad, R, Contreras-Guerrero, R, Kirsch, P, Jammy, R, Plummer, J & Saraswat, KC 2013, Optimal device architecture and hetero-integration scheme for III-V CMOS. in 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers., 6576683, Digest of Technical Papers - Symposium on VLSI Technology, pp. T54-T55, 2013 Symposium on VLSI Technology, VLSIT 2013, Kyoto, Japan, 11/06/13.

Optimal device architecture and hetero-integration scheme for III-V CMOS. / Yuan, Ze; Kumar, Archana; Chen, Chien Yu et al.
2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers. 2013. p. T54-T55 6576683 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - Optimal device architecture and hetero-integration scheme for III-V CMOS

AU - Yuan, Ze

AU - Kumar, Archana

AU - Chen, Chien Yu

AU - Nainani, Aneesh

AU - Griffin, Peter

AU - Wang, Albert

AU - Wang, Wei

AU - Wong, Man Hoi

AU - Droopad, Ravi

AU - Contreras-Guerrero, Rocio

AU - Kirsch, Paul

AU - Jammy, Raj

AU - Plummer, James

AU - Saraswat, Krishna C.

PY - 2013

Y1 - 2013

N2 - Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon [2]. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.

AB - Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon [2]. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.

UR - https://www.scopus.com/pages/publications/84883343471

M3 - Conference Paper published in a book

AN - SCOPUS:84883343471

SN - 9784863483477

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - T54-T55

BT - 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers

T2 - 2013 Symposium on VLSI Technology, VLSIT 2013

Y2 - 11 June 2013 through 13 June 2013

ER -

Optimal device architecture and hetero-integration scheme for III-V CMOS

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