Parallel electronic circuit simulation on the IPSC system.

Chen Ping Yuan; Robert Lucas; Philip Chan; Robert Dutton

Parallel electronic circuit simulation on the IPSC system.

Chen Ping Yuan^*, Robert Lucas, Philip Chan, Robert Dutton

^*Corresponding author for this work

Research output: Contribution to journal › Conference article published in journal › peer-review

5 Citations (Scopus)

Abstract

A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.

Original language	English
Pages (from-to)	6.5/1-4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1988
Externally published	Yes

Cite this

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title = "Parallel electronic circuit simulation on the IPSC system.",

abstract = "A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.",

author = "Yuan, \{Chen Ping\} and Robert Lucas and Philip Chan and Robert Dutton",

year = "1988",

language = "English",

pages = "6.5/1--4",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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TY - JOUR

T1 - Parallel electronic circuit simulation on the IPSC system.

AU - Yuan, Chen Ping

AU - Lucas, Robert

AU - Chan, Philip

AU - Dutton, Robert

PY - 1988

Y1 - 1988

N2 - A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.

AB - A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.

UR - https://www.scopus.com/pages/publications/0024143390

M3 - Conference article published in journal

AN - SCOPUS:0024143390

SN - 0886-5930

SP - 6.5/1-4

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

ER -

Parallel electronic circuit simulation on the IPSC system.

Abstract

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