Performance and Reliability Design Issues for Deep-Submicrometer MOSFET's

A comprehensive study of performance and reliability design issues for deep-submicrometer MOSFET's is presented. The following device design constraints are examined: threshold voltage variation due to short-channel and drain-induced-barrier-lowering effects, off-state leakage current due to punchthrough and gate-induced drain leakage, hot-carrier effects such as hot-electron degradation and avalanche breakdown, and time-dependent dielectric breakdown. In addition, the following performance criteria are examined: current-driving capability, ring-oscillator switching speed, and small-signal voltage gain. The impact that each of these factors has on the allowable choice of MOSFET channel length, oxide thickness, and power supply voltage is examined. Based on experimental results, a set of design curves, using a set of typical performance and reliability criteria, is presented for deep-submicrometer non-LDD n-channel devices. From these curves, the relative importance of each particular performance/reliability mechanism for a given technology and design criteria can be compared. Because the performance and reliability issues addressed in this study are also relevant to other MOSFET technologies, the design guidelines can also be extended to other technologies, including p-channel and LDD devices.