Performance Assessment of Stacked Monolayer WSe2 GAA NSFETs for Sub-5 nm Nodes

Ran Huo; Shijun Ou; Yihong Sun; Zichao Ma; Mansun Chan; Changjian Zhou

doi:10.1109/EDSSC64492.2025.11182883

Performance Assessment of Stacked Monolayer WSe₂ GAA NSFETs for Sub-5 nm Nodes

Ran Huo, Shijun Ou, Yihong Sun, Zichao Ma, Mansun Chan, Changjian Zhou^*

^*Corresponding author for this work

Department of Electronic and Computer Engineering

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

Abstract

D materials have received great research interest as promising candidates to extend Moore's Law for sub- 5 nm technology nodes. In particular, WSe₂ exhibits bipolar transport characteristics, making it highly suitable for constructing future Complementary FETs (CFETs) and stacked CMOS circuits. In this work, p-type stacked WSe₂ and Si GAA nanosheet (NS) FETs at N5 ~ N0.5 and ultra-scaled gate lengths are implemented and their performances are assessed by 3D TCAD simulations with careful experimental calibrations. WSe₂ NSFETs can outperform the Si counterparts in terms of exceptional ON-current (∼ 893.2 μ A/μ m) with OFF-current tightly controlled at 0.1 ∼ 1 fA/μm, near-ideal SS (~60.39 mV/dec), and negligible DIBL (~5.927 mV/V) for sub- 5 nm technology nodes. These metrics reach or even exceed the high-density (HD) projections from IRDS 2023 and the performance remains consistent and remarkable under aggressive scaling of the gate length, which underscores the potential for future advanced CFETs based on the same material.

Original language	English
Title of host publication	Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	159-162
Number of pages	4
ISBN (Electronic)	9798331522087
ISBN (Print)	9798331522094
DOIs	https://doi.org/10.1109/EDSSC64492.2025.11182883
Publication status	Published - 7 Oct 2025
Event	16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025 - Yinchuan, China Duration: 13 Jun 2025 → 15 Jun 2025

Publication series

Name	Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025

Conference

Conference	16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025
Country/Territory	China
City	Yinchuan
Period	13/06/25 → 15/06/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

WSe
Sub-5 nm
GAA NSFET
TCAD

Access to Document

10.1109/EDSSC64492.2025.11182883

Cite this

Huo, R., Ou, S., Sun, Y., Ma, Z., Chan, M., & Zhou, C. (2025). Performance Assessment of Stacked Monolayer WSe₂ GAA NSFETs for Sub-5 nm Nodes. In Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025 (pp. 159-162). Article 11182883 (Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC64492.2025.11182883

Huo, Ran ; Ou, Shijun ; Sun, Yihong et al. / Performance Assessment of Stacked Monolayer WSe₂ GAA NSFETs for Sub-5 nm Nodes. Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025. Institute of Electrical and Electronics Engineers Inc., 2025. pp. 159-162 (Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025).

@inproceedings{b4ffc427f3d14810a439dbad7732a64f,

title = "Performance Assessment of Stacked Monolayer WSe2 GAA NSFETs for Sub-5 nm Nodes",

abstract = "D materials have received great research interest as promising candidates to extend Moore's Law for sub- 5 nm technology nodes. In particular, WSe2 exhibits bipolar transport characteristics, making it highly suitable for constructing future Complementary FETs (CFETs) and stacked CMOS circuits. In this work, p-type stacked WSe2 and Si GAA nanosheet (NS) FETs at N5 \textasciitilde{} N0.5 and ultra-scaled gate lengths are implemented and their performances are assessed by 3D TCAD simulations with careful experimental calibrations. WSe2 NSFETs can outperform the Si counterparts in terms of exceptional ON-current (∼ 893.2 μ A/μ m) with OFF-current tightly controlled at 0.1 ∼ 1 fA/μm, near-ideal SS (\textasciitilde{}60.39 mV/dec), and negligible DIBL (\textasciitilde{}5.927 mV/V) for sub- 5 nm technology nodes. These metrics reach or even exceed the high-density (HD) projections from IRDS 2023 and the performance remains consistent and remarkable under aggressive scaling of the gate length, which underscores the potential for future advanced CFETs based on the same material.",

keywords = "WSe, Sub-5 nm, GAA NSFET, TCAD",

author = "Ran Huo and Shijun Ou and Yihong Sun and Zichao Ma and Mansun Chan and Changjian Zhou",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025 ; Conference date: 13-06-2025 Through 15-06-2025",

year = "2025",

month = oct,

day = "7",

doi = "10.1109/EDSSC64492.2025.11182883",

language = "English",

isbn = "9798331522094",

series = "Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "159--162",

booktitle = "Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025",

}

Huo, R, Ou, S, Sun, Y, Ma, Z, Chan, M & Zhou, C 2025, Performance Assessment of Stacked Monolayer WSe₂ GAA NSFETs for Sub-5 nm Nodes. in Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025., 11182883, Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025, Institute of Electrical and Electronics Engineers Inc., pp. 159-162, 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025, Yinchuan, China, 13/06/25. https://doi.org/10.1109/EDSSC64492.2025.11182883

Performance Assessment of Stacked Monolayer WSe₂ GAA NSFETs for Sub-5 nm Nodes. / Huo, Ran; Ou, Shijun; Sun, Yihong et al.
Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025. Institute of Electrical and Electronics Engineers Inc., 2025. p. 159-162 11182883 (Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - Performance Assessment of Stacked Monolayer WSe2 GAA NSFETs for Sub-5 nm Nodes

AU - Huo, Ran

AU - Ou, Shijun

AU - Sun, Yihong

AU - Ma, Zichao

AU - Chan, Mansun

AU - Zhou, Changjian

PY - 2025/10/7

Y1 - 2025/10/7

N2 - D materials have received great research interest as promising candidates to extend Moore's Law for sub- 5 nm technology nodes. In particular, WSe2 exhibits bipolar transport characteristics, making it highly suitable for constructing future Complementary FETs (CFETs) and stacked CMOS circuits. In this work, p-type stacked WSe2 and Si GAA nanosheet (NS) FETs at N5 ~ N0.5 and ultra-scaled gate lengths are implemented and their performances are assessed by 3D TCAD simulations with careful experimental calibrations. WSe2 NSFETs can outperform the Si counterparts in terms of exceptional ON-current (∼ 893.2 μ A/μ m) with OFF-current tightly controlled at 0.1 ∼ 1 fA/μm, near-ideal SS (~60.39 mV/dec), and negligible DIBL (~5.927 mV/V) for sub- 5 nm technology nodes. These metrics reach or even exceed the high-density (HD) projections from IRDS 2023 and the performance remains consistent and remarkable under aggressive scaling of the gate length, which underscores the potential for future advanced CFETs based on the same material.

AB - D materials have received great research interest as promising candidates to extend Moore's Law for sub- 5 nm technology nodes. In particular, WSe2 exhibits bipolar transport characteristics, making it highly suitable for constructing future Complementary FETs (CFETs) and stacked CMOS circuits. In this work, p-type stacked WSe2 and Si GAA nanosheet (NS) FETs at N5 ~ N0.5 and ultra-scaled gate lengths are implemented and their performances are assessed by 3D TCAD simulations with careful experimental calibrations. WSe2 NSFETs can outperform the Si counterparts in terms of exceptional ON-current (∼ 893.2 μ A/μ m) with OFF-current tightly controlled at 0.1 ∼ 1 fA/μm, near-ideal SS (~60.39 mV/dec), and negligible DIBL (~5.927 mV/V) for sub- 5 nm technology nodes. These metrics reach or even exceed the high-density (HD) projections from IRDS 2023 and the performance remains consistent and remarkable under aggressive scaling of the gate length, which underscores the potential for future advanced CFETs based on the same material.

KW - WSe

KW - Sub-5 nm

KW - GAA NSFET

KW - TCAD

UR - https://www.scopus.com/pages/publications/105019936726

U2 - 10.1109/EDSSC64492.2025.11182883

DO - 10.1109/EDSSC64492.2025.11182883

M3 - Conference Paper published in a book

AN - SCOPUS:105019936726

SN - 9798331522094

T3 - Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025

SP - 159

EP - 162

BT - Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025

Y2 - 13 June 2025 through 15 June 2025

ER -

Huo R, Ou S, Sun Y, Ma Z, Chan M, Zhou C. Performance Assessment of Stacked Monolayer WSe₂ GAA NSFETs for Sub-5 nm Nodes. In Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025. Institute of Electrical and Electronics Engineers Inc. 2025. p. 159-162. 11182883. (Proceedings of the 16th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2025). doi: 10.1109/EDSSC64492.2025.11182883