PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77 % and 97 % as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.