Practical compact modeling approaches and options for sub-0.1 μm CMOS technologies

This paper attempts to provide a general overview and guideline to develop a practical model for CMOS devices in the sub-0.1μm generations. It starts by giving an overview of the different modeling options including the charge-based approach, the surface potential based approach, and the conductance-based approach. Their relative advantages and weaknesses will be discussed. The evolution of the BSIM models from its first generation to the most recent release will be used as an example for the development of a practical device model. It will be followed by a discussion on how the accelerated technology development may impact the traditional modeling methodologies. A new paradigm to incorporate modern software engineering methodology to shorten model development cycle will be presented.