Process-Dependent Performance of Recessed-Gate Enhancement-Mode GaN p-FET

There is a strong demand for GaN complementary logic (CL) circuits and power integrated circuits (PICs). The E-mode p-GaN gate high electron mobility transistor (HEMT) platform is a promising solution for GaN CL circuits. Compared to the commercialized E-mode GaN n-FET (i.e., the p-GaN gate HEMT), the E-mode GaN p-FET has fallen far behind. To achieve E-mode operation, gate recess is a common approach, but the channel thickness (t_ch) and the surface roughness (R_q) of etched p-GaN significantly influence the performance of devices. This work investigates GaN p-FETs with different gate recess depths. A pre-treatment of the etched p-GaN surface is used to smooth the etched p-GaN surface. During the fabrication, t_ch is found to be a critical process parameter that influences the performance of devices. As the t_ch decreases, a more robust E-mode operation (i.e., a more negative V_th) is achieved. However, this leads to an increase in on-resistance (R_on). When t_ch = 8.5 nm, the fabricated E-mode GaN p-FET exhibits a V_th of −1.1 V and a high I_D-max of 5.1 mA mm⁻¹. Compared to the E-modep-FET without pre-treatment, the current density more than doubles. This work advances the development of p-FETs on the standard E-mode p-GaN gate HEMT platform.