Abstract
In this paper, a methodology for generating worst-case SPICE files is presented. This methodology is based upon the identification and evaluation of circuit building blocks within a design. Correlations between these blocks will be determined for a specific circuit variable. The results show there is a high degree of correlation between NAND, NOR, inverter logic gates and NAND gate implemented in Complementary Pass Transistor Logic (CPL) with regards to speed and power dissipation. A method of resolving multiple SPICE files is also presented which produces a realistic prediction of circuit performance.
| Original language | English |
|---|---|
| Pages (from-to) | 375-378 |
| Number of pages | 4 |
| Journal | Proceedings of the Custom Integrated Circuits Conference |
| Publication status | Published - 1995 |
| Externally published | Yes |
| Event | Proceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 1 May 1995 → 4 May 1995 |