Abstract
The continuous scaling of semiconductor devices has driven significant advancements in the industry, but also introduced challenges such as short channel effects and higher metal resistance. This paper explores the development of Complementary Field-Effect Transistors (CFETs), which stack n-type and p-type FETs to enhance performance and reduce power consumption. The historical evolution, technical challenges, and future potential of CFETs are discussed, highlighting innovative processes like back-side power rail integration and the use of 2D materials for improved device efficiency.
| Original language | English |
|---|---|
| Title of host publication | 2024 IEEE 17th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024 |
| Editors | Fan Ye, Xiaona Zhu, Ting Ao Tang |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798350361834 |
| DOIs | |
| Publication status | Published - 2024 |
| Event | 17th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024 - Zhuhai, China Duration: 22 Oct 2024 → 25 Oct 2024 |
Publication series
| Name | 2024 IEEE 17th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024 |
|---|
Conference
| Conference | 17th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024 |
|---|---|
| Country/Territory | China |
| City | Zhuhai |
| Period | 22/10/24 → 25/10/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- 2D transistor
- CFET
- nano-sheet (key words)
- stacked transistors
