Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs

Mohamed Soliman; Antti Nurmi; Syed Mohsin Abbas

doi:10.1109/ISCAS56072.2025.11043609

Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs

Mohamed Soliman^*, Antti Nurmi, Syed Mohsin Abbas

^*Corresponding author for this work

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

Abstract

Modern commercial Multi-Processor Systems-Onchips (MPSoCs), targeted for smartphones as well as embedded Artificial Intelligence (AI) and Internet-Of-Things (IoT) applications, require camera interfaces that support the CSI-2 standard and are reconfigurable to support various image data types and throughput requirements. However, existing State-Of-the-Art (SoA) implementations of reconfigurable camera interfaces are proprietary and closed-source.This work proposes, to the best of our knowledge, the first open-source implementation of a reconfigurable image acquisition and processing platform for MPSoC integration. The proposed design is implemented and verified on both FPGA (Zynq ZCU104 FPGA) and ASIC (TSMC 22nm) platforms. The hardware implementation results depict that the proposed design can support a throughput of 9.6 Gbps for streaming 4K resolution images.

Original language	English
Title of host publication	ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350356830
DOIs	https://doi.org/10.1109/ISCAS56072.2025.11043609
Publication status	Published - 2025
Externally published	Yes
Event	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom Duration: 25 May 2025 → 28 May 2025

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Country/Territory	United Kingdom
City	London
Period	25/05/25 → 28/05/25

Bibliographical note

Publisher Copyright:
© 2025 IEEE.

Keywords

ASIC
CSI-2
Camera Interface
FPGA
Multi-Processor Systems-On-Chips (MPSoCs)
open-source IP

Access to Document

10.1109/ISCAS56072.2025.11043609

Cite this

Soliman, M., Nurmi, A., & Abbas, S. M. (2025). Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs. In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS56072.2025.11043609

@inproceedings{6a329194274d443abfd67cbda9508711,

title = "Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs",

abstract = "Modern commercial Multi-Processor Systems-Onchips (MPSoCs), targeted for smartphones as well as embedded Artificial Intelligence (AI) and Internet-Of-Things (IoT) applications, require camera interfaces that support the CSI-2 standard and are reconfigurable to support various image data types and throughput requirements. However, existing State-Of-the-Art (SoA) implementations of reconfigurable camera interfaces are proprietary and closed-source.This work proposes, to the best of our knowledge, the first open-source implementation of a reconfigurable image acquisition and processing platform for MPSoC integration. The proposed design is implemented and verified on both FPGA (Zynq ZCU104 FPGA) and ASIC (TSMC 22nm) platforms. The hardware implementation results depict that the proposed design can support a throughput of 9.6 Gbps for streaming 4K resolution images.",

keywords = "ASIC, CSI-2, Camera Interface, FPGA, Multi-Processor Systems-On-Chips (MPSoCs), open-source IP",

author = "Mohamed Soliman and Antti Nurmi and Abbas, \{Syed Mohsin\}",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",

year = "2025",

doi = "10.1109/ISCAS56072.2025.11043609",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",

}

Soliman, M, Nurmi, A & Abbas, SM 2025, Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs. in ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, 25/05/25. https://doi.org/10.1109/ISCAS56072.2025.11043609

Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs. / Soliman, Mohamed; Nurmi, Antti; Abbas, Syed Mohsin.
ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

TY - GEN

T1 - Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs

AU - Soliman, Mohamed

AU - Nurmi, Antti

AU - Abbas, Syed Mohsin

PY - 2025

Y1 - 2025

N2 - Modern commercial Multi-Processor Systems-Onchips (MPSoCs), targeted for smartphones as well as embedded Artificial Intelligence (AI) and Internet-Of-Things (IoT) applications, require camera interfaces that support the CSI-2 standard and are reconfigurable to support various image data types and throughput requirements. However, existing State-Of-the-Art (SoA) implementations of reconfigurable camera interfaces are proprietary and closed-source.This work proposes, to the best of our knowledge, the first open-source implementation of a reconfigurable image acquisition and processing platform for MPSoC integration. The proposed design is implemented and verified on both FPGA (Zynq ZCU104 FPGA) and ASIC (TSMC 22nm) platforms. The hardware implementation results depict that the proposed design can support a throughput of 9.6 Gbps for streaming 4K resolution images.

AB - Modern commercial Multi-Processor Systems-Onchips (MPSoCs), targeted for smartphones as well as embedded Artificial Intelligence (AI) and Internet-Of-Things (IoT) applications, require camera interfaces that support the CSI-2 standard and are reconfigurable to support various image data types and throughput requirements. However, existing State-Of-the-Art (SoA) implementations of reconfigurable camera interfaces are proprietary and closed-source.This work proposes, to the best of our knowledge, the first open-source implementation of a reconfigurable image acquisition and processing platform for MPSoC integration. The proposed design is implemented and verified on both FPGA (Zynq ZCU104 FPGA) and ASIC (TSMC 22nm) platforms. The hardware implementation results depict that the proposed design can support a throughput of 9.6 Gbps for streaming 4K resolution images.

KW - ASIC

KW - CSI-2

KW - Camera Interface

KW - FPGA

KW - Multi-Processor Systems-On-Chips (MPSoCs)

KW - open-source IP

UR - http://www.scopus.com/inward/record.url?scp=105010576728&partnerID=8YFLogxK

U2 - 10.1109/ISCAS56072.2025.11043609

DO - 10.1109/ISCAS56072.2025.11043609

M3 - Conference Paper published in a book

AN - SCOPUS:105010576728

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025

Y2 - 25 May 2025 through 28 May 2025

ER -

Reconfigurable Image Acquisition and Processing Subsystem for MPSoCs

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Keywords

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