Reduced-complexity concurrent systolic implementation of the discrete sine transform

P. K. Meher; A. P. Vinod; J. C. Patra; M. N.S. Swamy

doi:10.1109/APCCAS.2006.342535

Reduced-complexity concurrent systolic implementation of the discrete sine transform

P. K. Meher, A. P. Vinod, J. C. Patra, M. N.S. Swamy

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

4 Citations (Scopus)

Abstract

In this paper, a reduced complexity algorithm for computation of the discrete sine transform (DST) is presented. The proposed algorithm can be used to compute an N-point DST from two pairs of [(M - 1)/2]-point identical cyclic convolutions, where M is a prime number and M = N/2. A regular and locally connected linear systolic array architecture is also presented for concurrent pipelined VLSI implementation of all the four cyclic convolutions. The proposed structure is not only simpler, but also involves significantly less area-time complexity compared to that of the existing convolution-based DST structures. Unlike some of the existing structures, it does not need any control tag-bits for implementation of convolutionlike operations.

Original language	English
Title of host publication	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages	1535-1538
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2006.342535
Publication status	Published - 2006
Externally published	Yes
Event	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore Duration: 4 Dec 2006 → 6 Dec 2006

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference	APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	Singapore
Period	4/12/06 → 6/12/06

Keywords

Digital signal processing (DSP) chip
Discrete sine transform (DST)
Systolic array
VLSI

Access to Document

10.1109/APCCAS.2006.342535

Cite this

Meher, P. K., Vinod, A. P., Patra, J. C., & Swamy, M. N. S. (2006). Reduced-complexity concurrent systolic implementation of the discrete sine transform. In APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems (pp. 1535-1538). Article 4145697 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2006.342535

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title = "Reduced-complexity concurrent systolic implementation of the discrete sine transform",

abstract = "In this paper, a reduced complexity algorithm for computation of the discrete sine transform (DST) is presented. The proposed algorithm can be used to compute an N-point DST from two pairs of [(M - 1)/2]-point identical cyclic convolutions, where M is a prime number and M = N/2. A regular and locally connected linear systolic array architecture is also presented for concurrent pipelined VLSI implementation of all the four cyclic convolutions. The proposed structure is not only simpler, but also involves significantly less area-time complexity compared to that of the existing convolution-based DST structures. Unlike some of the existing structures, it does not need any control tag-bits for implementation of convolutionlike operations.",

keywords = "Digital signal processing (DSP) chip, Discrete sine transform (DST), Systolic array, VLSI",

author = "Meher, \{P. K.\} and Vinod, \{A. P.\} and Patra, \{J. C.\} and Swamy, \{M. N.S.\}",

year = "2006",

doi = "10.1109/APCCAS.2006.342535",

language = "English",

isbn = "1424403871",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "1535--1538",

booktitle = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 04-12-2006 Through 06-12-2006",

}

Meher, PK, Vinod, AP, Patra, JC & Swamy, MNS 2006, Reduced-complexity concurrent systolic implementation of the discrete sine transform. in APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems., 4145697, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1535-1538, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 4/12/06. https://doi.org/10.1109/APCCAS.2006.342535

Reduced-complexity concurrent systolic implementation of the discrete sine transform. / Meher, P. K.; Vinod, A. P.; Patra, J. C. et al.
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems. 2006. p. 1535-1538 4145697 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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T1 - Reduced-complexity concurrent systolic implementation of the discrete sine transform

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AU - Vinod, A. P.

AU - Patra, J. C.

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N2 - In this paper, a reduced complexity algorithm for computation of the discrete sine transform (DST) is presented. The proposed algorithm can be used to compute an N-point DST from two pairs of [(M - 1)/2]-point identical cyclic convolutions, where M is a prime number and M = N/2. A regular and locally connected linear systolic array architecture is also presented for concurrent pipelined VLSI implementation of all the four cyclic convolutions. The proposed structure is not only simpler, but also involves significantly less area-time complexity compared to that of the existing convolution-based DST structures. Unlike some of the existing structures, it does not need any control tag-bits for implementation of convolutionlike operations.

AB - In this paper, a reduced complexity algorithm for computation of the discrete sine transform (DST) is presented. The proposed algorithm can be used to compute an N-point DST from two pairs of [(M - 1)/2]-point identical cyclic convolutions, where M is a prime number and M = N/2. A regular and locally connected linear systolic array architecture is also presented for concurrent pipelined VLSI implementation of all the four cyclic convolutions. The proposed structure is not only simpler, but also involves significantly less area-time complexity compared to that of the existing convolution-based DST structures. Unlike some of the existing structures, it does not need any control tag-bits for implementation of convolutionlike operations.

KW - Digital signal processing (DSP) chip

KW - Discrete sine transform (DST)

KW - Systolic array

KW - VLSI

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ER -

Reduced-complexity concurrent systolic implementation of the discrete sine transform

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