Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping

Dongli Zhang; Mingxing Wang; Huaisheng Wang; Yong Wu; Haiqin Zhou; Jin He

doi:10.1109/IPFA.2015.7224412

Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping

Dongli Zhang, Mingxing Wang, Huaisheng Wang, Yong Wu, Haiqin Zhou, Jin He

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

2 Citations (Scopus)

Abstract

Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors. It is proposed to be due to local electron trapping in the gate oxide near the drain after drain-bias sweeping such that the gate bias effect is screened. The effects of drain bias sweeping can be achieved equivalently by a DC bias stress. It is further proposed that pulsed drain bias sweeping is a most reliable method to achieve suppressed GIDL current and unaffected subthreshold and on-state characteristics.

Original language	English
Title of host publication	Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	407-410
Number of pages	4
ISBN (Electronic)	9781479999286, 9781479999286
DOIs	https://doi.org/10.1109/IPFA.2015.7224412
Publication status	Published - 25 Aug 2015
Externally published	Yes
Event	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 - Hsinchu, Taiwan, Province of China Duration: 29 Jun 2015 → 2 Jul 2015

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume	2015-August

Conference

Conference	22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	29/06/15 → 2/07/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

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10.1109/IPFA.2015.7224412

Cite this

Zhang, D., Wang, M., Wang, H., Wu, Y., Zhou, H., & He, J. (2015). Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping. In Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 (pp. 407-410). Article 7224412 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPFA.2015.7224412

Zhang, Dongli ; Wang, Mingxing ; Wang, Huaisheng et al. / Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping. Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 407-410 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

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title = "Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping",

abstract = "Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors. It is proposed to be due to local electron trapping in the gate oxide near the drain after drain-bias sweeping such that the gate bias effect is screened. The effects of drain bias sweeping can be achieved equivalently by a DC bias stress. It is further proposed that pulsed drain bias sweeping is a most reliable method to achieve suppressed GIDL current and unaffected subthreshold and on-state characteristics.",

author = "Dongli Zhang and Mingxing Wang and Huaisheng Wang and Yong Wu and Haiqin Zhou and Jin He",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015 ; Conference date: 29-06-2015 Through 02-07-2015",

year = "2015",

month = aug,

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doi = "10.1109/IPFA.2015.7224412",

language = "English",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

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Zhang, D, Wang, M, Wang, H, Wu, Y, Zhou, H & He, J 2015, Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping. in Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015., 7224412, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. 407-410, 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015, Hsinchu, Taiwan, Province of China, 29/06/15. https://doi.org/10.1109/IPFA.2015.7224412

Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping. / Zhang, Dongli; Wang, Mingxing; Wang, Huaisheng et al.
Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 407-410 7224412 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA; Vol. 2015-August).

Research output: Chapter in Book/Conference Proceeding/Report › Conference Paper published in a book › peer-review

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AU - He, Jin

PY - 2015/8/25

Y1 - 2015/8/25

N2 - Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors. It is proposed to be due to local electron trapping in the gate oxide near the drain after drain-bias sweeping such that the gate bias effect is screened. The effects of drain bias sweeping can be achieved equivalently by a DC bias stress. It is further proposed that pulsed drain bias sweeping is a most reliable method to achieve suppressed GIDL current and unaffected subthreshold and on-state characteristics.

AB - Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors. It is proposed to be due to local electron trapping in the gate oxide near the drain after drain-bias sweeping such that the gate bias effect is screened. The effects of drain bias sweeping can be achieved equivalently by a DC bias stress. It is further proposed that pulsed drain bias sweeping is a most reliable method to achieve suppressed GIDL current and unaffected subthreshold and on-state characteristics.

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Zhang D, Wang M, Wang H, Wu Y, Zhou H, He J. Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping. In Proceedings of the 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 407-410. 7224412. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2015.7224412

Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping

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