TY - JOUR
T1 - Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits
AU - Kumar, Ranjith
AU - Kursun, Volkan
PY - 2006/10
Y1 - 2006/10
N2 - The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented.
AB - The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented.
KW - High temperature speed
KW - supply voltage scaling
KW - temperature variations
UR - https://www.webofscience.com/wos/woscc/full-record/WOS:000241438800018
UR - https://openalex.org/W2153273695
UR - https://www.scopus.com/pages/publications/33750596850
U2 - 10.1109/TCSII.2006.882218
DO - 10.1109/TCSII.2006.882218
M3 - Journal Article
SN - 1549-7747
VL - 53
SP - 1078
EP - 1082
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 10
ER -