Robust delay-fault test generation and synthesis for testability under a standard scan design methodology

It is the authors' belief that one of the principal obstacles to the wider practical application of test generation for faults in enhanced fault models such as the robust path-delay-fault and gate-delay-fault models is the inability to robustly delay-test a sequential circuit using a standard-scan methodology. This problem is addressed, and a variety of techniques that can be used to generate robust delay test for sequential circuits is given. It is shown how various synthesis techniques can be applied to improve the robust delay-fault testability of circuits in a standard scan methodology. It appears that entire integrated circuits of moderate complexity can be synthesized for highly (nearly 100%) robust gate-delay-fault coverage, using these techniques.